ECE2030b - HW-5 v.2 Due Monday 10/21 during class.

Problem 1. Using Finite State Machine techniques, design a circuit to:

   Detect when sequential input X delivers 3 logic 1's in a row.
   Do not detect overlapping sequences.

Example:
   Input:  01101111011111001111110
   Output: 00000010000100000010010

A. Draw a State Diagram showing all possible states and transitions.

B. Draw a logic table for the Next State bits (Ni) and the Output bit (Q), as a function of Present State bits (Pi) and Input bit (X).

C. Draw Karnaugh maps for the separate outputs, Ni and Q.

D. Draw a logic diagram showing the necessary registers and combinatorial logic blocks.