Thesis Abstract:
3D integration technology has the potential to simultaneously address many of the challenges faced by the microprocessor industry. By placing the microprocessor circuits in vertically stacked layers and providing vertical connectivity with short interconnects, 3D integration technology greatly reduces wire lengths and the resulting delay and power consumption. I have proposed 3D-integrated designs of the microprocessor components, such as caches, register files, arithmetic units, and instruction schedulers, based on partitioning the logic circuitry (SRAM/CAM arrays, full-adder, shifter) and/or the wiring (wordlines, bitlines, and read/write ports). Using the data and insights gained from the designs of the 3D-integrated circuits, I proposed high-performance 3D-integrated microprocessors and quantified the impact on frequency, power, area footprint, and temperature. A 3D-integrated microprocessor design of a clustered architecture (based on the Alpha 21364 processor) demonstrated two different approaches to improve performance (improved clock frequency and improved instructions per clock cycle). Another 3D-integrated microprocessor design of a dual-core architecture (based on the Intel Core2 Duo processor) combined existing microarchitectural techniques that exploit data-width locality to address the challenges of power density and temperature. The 3D-integrated processors provide a significant performance benefit over the planar processors while simultaneously reducing the total power and the area footprint. The simultaneous benefits in multiple objectives makes 3D-integration a highly desirable technology for use in building future microprocessors. One of the key contributions of my thesis is the temperature analysis that shows that the worst-case temperature on 3D-integrated processors is within manageable limits and is not a show-stopper as previously expected. I believe that the 3D-integration technology will experience wide-spread deployment in the near future and that it will extend the applicability of the Moore's law for a few more generations.
Publications
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Conferences
Kiran Puttaswamy and Gabriel H. Loh,
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors,
(pdf)
in the Proceedings of the ACM Design Automation Conference (DAC), pp. 622-625, June 4-8, 2007, San Diego, CA, USA.
Kiran Puttaswamy and Gabriel H. Loh,
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors,
(pdf)
(ppt)
in the Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), pp. 193-204, February 10-14, 2007, Phoenix, AZ, USA.
Chinnakrishnan Ballapuram, Kiran Puttaswamy, Gabriel H. Loh and Hsien-Hsin S. Lee,
Entropy-based Low Power Data TLB Design,
(pdf)
in the Proceedings of the ACM/IEEE Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), pp. 304-311, October 23-25, 2006, Seoul, South Korea.
Kiran Puttaswamy and Gabriel H. Loh,
The Impact of 3-Dimensional Integration on the Design of Arithmetic Units,
(pdf)
in the Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4951-4954, May 21-24, 2006, Kos, Greece.
Kiran Puttaswamy and Gabriel H. Loh,
Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor,
(pdf)
in the Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 19-24, April 30-May 2, 2006, Philadelphia, PA, USA.
Kiran Puttaswamy and Gabriel H. Loh,
Dynamic Instruction Schedulers in a 3-Dimensional Integration Technology,
(pdf)
in the Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 153-158, April 30-May 2, 2006, Philadelphia, PA, USA.
Kiran Puttaswamy and Gabriel H. Loh,
Implementing Register File for High-Performance Microprocessors in a Die-Stacked (3D) Technology,
(pdf)
in the Proceedings of the IEEE International Symposium on VLSI (ISVLSI), pp. 384-389, March 1-3, 2006, Karlsruhe, Germany.
Kiran Puttaswamy and Gabriel H. Loh,
Implementing Caches in a 3D Technology for High Performance Processors,
(pdf)
in the Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 525-532, October 2-5, 2005, San Jose, CA, USA.
Jinwoo Kim and Kiran Puttaswamy,
Possibility and Limitation of a Hardware-Assisted Data Prefetching Framework Using Off-Line Training of Markovian Predictors,
in the Proceedings of the International Conference on Computer Design (CDES), June 27-30, 2005, Las Vegas, NV, USA.
Kiran Puttaswamy, Kresten McGrath, Satya Vadlamani and Ravi Kolagotla,
High speed high accuracy power estimation methodology for next generation system-on-a-chip (SoC) micro-architectures,
in the Proceedings of the Intel Design and Test Technology Conference (DTTC), 2004, Portland, OR, USA.
Raghavan Sudhakar, Kiran Puttaswamy and Ravi Kolagotla,
Efficient GSM-AMR channel decoding for next generation DSP by improved Traceback,
in the Proceedings of the Intel Design and Test Technology Conference (DTTC), 2004, Portland, OR, USA.
Kiran Puttaswamy, Dhinakarraj H. Gantala and Ravi Kolagotla
Power analysis of a VLIW DSP core on an embedded processor system-on-a-chip (SoC) using instruction set architecture features,
in the Proceedings of the Intel Design and Test Technology Conference (DTTC), 2003, Portland, OR, USA.
Kiran Puttaswamy, Jun-Cheol Park, Kyu-won Choi, Abhijit Chatterjee, Peeter Ellervee and Vincent John Mooney III,
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory,
in the Proceedings of the International Symposium on System Synthesis (ISSS), pp. 225-230, October 2-4, 2002, Tokyo, Japan.
Krishna V. Palem, Rodric M. Rabbah, Vincent John Mooney, Pinar Korkmaz and Kiran Puttaswamy,
Design space optimization of embedded memory systems via data remapping,
in the Proceedings of the ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems and Software and Compilers for Embedded Systems (LCTES-SCOPES), pp. 28-37, June 19-21, 2002, Berlin, Germany.
Lakshmi N. Chakrapani, Pinar Korkmaz, Vincent John Mooney III, Krishna V. Palem, Kiran Puttaswamy and W. F. Wong,
The Emerging Power Crisis in Embedded Processors: What can a Poor Compiler Do?,
in the Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), pp. 176-180, November 16-17, 2001, Atlanta, GA, USA.
Journals/Book Chapters
Kiran Puttaswamy, Peeter Ellervee, Vincent John Mooney, III, Krishna V. Palem, Weng-Fai Wong,
Lakshmi Narasimhan Chakrapani, Kyu-Won Choi, Yuvraj Singh Dhillon, Utku Diril, Pinar Korkmaz,
Kyoung-Keun Lee, Jun Cheol Park and Abhijit Chatterjee,
Power-performance trade-offs in second level memory used by an ARM-like RISC architecture,
(Publisher's site)
in the Springer Power Aware Computing Series, Ed: Robert Graybill and Rami Melhem, pp. 211 - 224, 2002.
Technical Reports
Rodric M. Rabbah, Kiran Puttaswamy and Suresh Cheemalavagu,
Design and Synthesis of a High Performance and Low Power Routing Switch for a Hypercube Network,
CREST Technical Report CREST-TR-02-08, October 2002.
Pinar Korkmaz, Kiran Puttaswamy and Vincent Mooney III,
Energy modeling of processor core and memory hierarchy using Synopsis and Kamble and Ghosh model,
CREST Technical Report CREST-TR-02-02, February 2002.
Krishna V. Palem, Rodric M. Rabbah, Vincent Mooney III, Pinar Korkmaz and Kiran Puttaswamy,
Power Optimization of Embedded Memory Systems via Data Remapping,
GATech Technical Report: GIT-CC-02-010.