Publisher: Prentice Hall , ISBN: 0-13-145735-7
Copyright: 2005, Format: Paper; 256 pp
This text focuses on presenting the basic features of the VHDL language in the context of its use for simulation. The text is targeted for use in sophomore and junior level courses in digital logic and computer architecture. The style of this text is intended to permit integration of the basic concepts underlying VHDL into existing courses without necessitating additional credit hours or courses for instruction. In order to fill the need for a companion text for digital logic and computer architecture courses and to serve as an early introduction to the basic language concepts the book must satisfy several criteria. First, it must relate VHDL concepts to those already familiar to the student. Students learn best when they can relate new concepts to ones with which they are already familiar. In this case we rely on concepts from the operation of digital circuits. Language features are motivated by the need to describe specific aspects of the operation of digital circuits, for example, events, propagation delays, and concurrency.
The following materials are provided for use with the text. If you would like to download all of the vugraphs you can do so with the following zip file.
Introduction [Vugraphs (ppt, pdf)]
This chapter provides a very brief introduction to the place hardware description languages employ in a typical digital system design flow and the genealogy of VHDL.
VHDL language constructs can be
related to digital system concepts that we are already familiar with. This
chapter lists fundamental physical and behavioral attributes of
digital systems. Language constructs to describe each attribute will be
introduced in subsequent chapters. The chapter concludes with a description of
the discrete event execution model that underlies the execution of the VHDL
Basic language constructs are
introduced by associating each construct with a physical or behavioral
attribute of digital systems. Existing knowledge of digital systems is
naturally transformed into executable VHDL descriptions.
In describing very large systems
we often wish to abstract or hide the details of digital logic implementation
while preserving the external behavior. Such a modeling approach can be
achieved in VHDL with higher level language constructs structured in processes.
The use of hierarchy and
abstraction is necessary to handle large designs and consequently requires the
introduction of new language constructs. A hierarchy of netlists is a
standard representation in traditional digital design tools and VHDL
provides language constructs for a textual description of such a hierarchy.
Abstraction is enabled in VHDL via
standard programming language concepts such as procedures, functions, packages
and libraries to enable design re-use, sharing, and ease of maintenance.
Text file input/output mechanisms
are used to enable the integration of the results of test generation tools and
the VHDL models under test. Basic error checking and testbench generation
techniques are also covered.
This chapter provides an intuition
about the practical aspects of VHDL environments: the terminology and mechanics
of organizing, building, simulating VHDL models.
A quick reference guide to the basic language syntax.
References to some excellent texts that cover more advanced features of the language.
Appendix A: Active HDL Tutorial
Appendix B: Standard VHDL Packages
An introduction to some common packages used in VHDL models.
Appendix E: A Starting Program Template
A program template illustrating the syntactical relationships between various VHDL constructs. A handy reference early in process of learning VHDL.