School of Electrical and Computer Engineering,
Georgia Institute of Technology,
777 Atlantic Drive,
Atlanta, Georgia 30332-0250 U.S.A.
Phone 404 276 4523
darshan AT ece DOT gatech DOT edu

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. Journal of Automated Reasoning, to appear.

• Jun Cheol Park, Vincent J. Mooney, Sudarshan K. Srinivasan. Combining Data Remapping and Voltage/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded Systems. Microelectronics Journal , 2003.

• Panagiotis Manolios, Sudarshan K. Srinivasan, and Daron Vroon. Automatic Memory Reductions for RTL-Level Verification. ACM-IEEE International Conference on Computer Aided Design (ICCAD'06), 2006

• Roma Kane, Panagiotis Manolios, and Sudarshan K. Srinivasan. Monolithic Verification of Deep Pipelines with Collapsed Flushing. ACM-IEEE Design, Automation, and Test in Europe (DATE'06) , 2006

• Panagiotis Manolios and Sudarshan K. Srinivasan. Verification of Executable Pipelined Machines with Bit-Level Interfaces. ACM-IEEE International Conference on Computer Aided Design (ICCAD'05) , November 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Complete Compositional Reasoning Framework for the Efficient Verification of Pipelined Machines. ACM-IEEE International Conference on Computer Aided Design (ICCAD'05) , November 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Computationally Efficient Method Based on Commitment Refinement Maps for Verifying Pipelined Machines. ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'05), 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. 13th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME'05), 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. Refinement Maps for Efficient Verification of Processor Models. Design Automation and Test in Europe (DATE'05), 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Suite of Hard ACL2 Theorems Arising in Refinement-Based Processor Verification. ACL2 Workshop (ACL2'04), 2004.

• Panagiotis Manolios and Sudarshan K. Srinivasan. Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB-Refinements. Design Automation and Test in Europe (DATE'04), 2004.

• Sudarshan K. Srinivasan, and Miroslav N. Velev Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Imprecise Data-Memory Exceptions. Formal Methods and Models for Codesign (MEMOCODE'03), 2003.

• Sudarshan K. Srinivasan, Jun Cheol Park, and Vincent J. Mooney. Combining Data Remapping and Voltage/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded Systems. Embedded System Codesign (ESCODES'02) , 2002.

• Panagiotis Manolios and Sudarshan K. Srinivasan. Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB-Refinements. CERCS TR# GIT-CERCS-03-17,, 2003.