Abstract: An ever larger variety of embedded ASICs are being designed and deployed that have both challenging performance requirements to process real-time audio or video signals, and tight energy constraints to allow them to operate in a portable manner. Specialized nonprogrammable hardware accelerators are often used in these systems to accelerate parts of the application that would run too slowly or consume too much power if implemented in software on an embedded programmable processor. Nonprogrammable accelerators are undesirable due to their lack of programmability and retargetability. As a result, new applications or extensions to existing applications often require complete re-designs of the accelerators. Further, there is little hardware re-use within an application due to the high degree of specialization. In this talk, the design of programmable loop accelerators is investigated. The approach combines a flexible hardware schema and a compiler-directed architecture synthesis process to create a design highly specialized to the target application, but programmable in nature.
Biography: Scott Mahlke is the Morris Wellman Faculty Development Assistant Professor in the Electrical Engineering and Computer Science Department at the University of Michigan. He received the Ph.D. degree from the University of Illinois in 1997. Prior to joining Michigan, he was a research scientist in the Compiler and Architecture Research Group at Hewlett-Packard Laboratories. His work has contributed to the development of the IMPACT and Trimaran compiler systems as well as the PICO synthesis system. His research interests include application specific processor design, compilation for high-performance processors, and computer architecture.
Abstract: The automatic translation of static nested loop programs to parallel Process Network specifications has been shown to be feasible and effective. A tool suite called Compaan is available for this purpose. Moreover, another tool suite called Laura is available for the mapping of Compaan Networks into Reconfigurable processors. All this has recently been extended to include Weakly Dynamic Programs which are frequently encountered in Signal Processing and Multimedia applications. The talk deals with these extensions.
Biography: Ed F. Deprettere is Professor at the Leiden Institute of Advanced Computer Science (LIACS), and head of the Leiden Embedded Research Center, (LERC).
Abstract: Increasing design and manufacturing costs are prompting a shift in electronic design from hardwired application-specific integrated circuits (ASICs) to the use of software on programmable platforms. In order to minimize the power and performance overhead of such platforms, domain or application-specific processors have been used. The development of such processors requires not only traditional electronic design automation tools but also processor-specific software tools such as compilers and instruction set simulators. In early development stages when multiple processor design points are explored, it is necessary to have the software tools synthesized from high level processor descriptions. This talk presents an approach that aims to automate the synthesis of these software tools. The foundation of the approach is a novel concurrency model, the operation state machine (OSM). The OSM model views a processor in two interacting levels: the operation level where instruction behavior is represented and the hardware level where resources required for instruction execution are managed. Through proper abstraction, the model significantly simplifies the specification of concurrency and control semantics without compromising flexibility. Based on the OSM model, we designed MESCAL Architecture Description Language (MADL). Software tools including cycle-accurate simulators, instruction set simulators, and disassemblers have been synthesized from MADL-based processor models. The MADL-based models have also been used to extract reservation tables for instruction schedulers in compilers. Experimental results show that the MADL-based approach is very effective in supporting these software tools and the synthesized simulators have competitive simulation speeds compared to their hand-coded counterparts.
Biography: Sharad Malik received the B. Tech. degree in Electrical Engineering from the Indian Institute of Technology, New Delhi, India in 1985 and the M.S. and Ph.D. degrees in Computer Science from the University of California, Berkeley in 1987 and 1990 respectively. Currently he is Professor in the Department of Electrical Engineering, Princeton University. His research spans all aspects of Electronic Design Automation. His current focus areas are the synthesis and verification of digital systems and embedded computer systems. He has received the President of India's Gold Medal for academic excellence (1985), the IBM Faculty Development Award (1991), an NSF Research Initiation Award (1992), Princeton University Rheinstein Faculty Award (1994), the NSF Young Investigator Award (1994), Best Paper Awards at the IEEE International Conference on Computer Design (1992), ACM/IEEE Design Automation Conference (1996), IEEE/ACM Design Automation and Test in Europe Conference (2003); the Walter C. Johnson Prize for Teaching Excellence (1993) and the Princeton University Engineering Council Excellence in Teaching Award (1993, 1994, 1995). He serves/has served on the program committees of DAC, ICCAD and ICCD and as the General Chair for DAC 2004. He is on the editorial boards of the Journal of VLSI Signal Processing, Design Automation for Embedded Systems and IEEE Design and Test. He is a fellow of the IEEE. He is currently serving as the Associate Director of the MARCO/DARPA Gigascale Systems Research Center, a multi-university effort directed towards defining and developing system design methodology with a ten year horizon. He has published numerous papers, book chapters and a book (Static Timing Analysis for Embedded Software) describing his research. His research in functional timing analysis and propositional satisfiability has been widely used in industrial electronic design automation tools.
Abstract: Increasing design and manufacturing costs are prompting a shift in electronic design from hardwired application-specific integrated circuits (ASICs) to the use of software on programmable platforms. In order to minimize the power and performance overhead of such platforms, domain or application-specific processors have been used. The development of such processors requires not only traditional electronic design automation tools but also processor-specific software tools such as compilers and instruction set simulators. In early development stages when multiple processor design points are explored, it is necessary to have the software tools synthesized from high level processor descriptions. This talk presents an approach that aims to automate the synthesis of these software tools. The foundation of the approach is a novel concurrency model, the operation state machine (OSM). The OSM model views a processor in two interacting levels: the operation level where instruction behavior is represented and the hardware level where resources required for instruction execution are managed. Through proper abstraction, the model significantly simplifies the specification of concurrency and control semantics without compromising flexibility. Based on the OSM model, we designed MESCAL Architecture Description Language (MADL). Software tools including cycle-accurate simulators, instruction set simulators, and disassemblers have been synthesized from MADL-based processor models. The MADL-based models have also been used to extract reservation tables for instruction schedulers in compilers. Experimental results show that the MADL-based approach is very effective in supporting these software tools and the synthesized simulators have competitive simulation speeds compared to their hand-coded counterparts.
Biography: Wei Qin is an assistant professor in the ECE Department of Boston University. He received his B.S. and M.S. degree from Fudan University in China, and his Ph.D. degree recently from Princeton University. His research interests include design tools for embedded systems and embedded processors, and design language for electronic systems.
Abstract: Recently, a number of designs for programmable architectures have been presented that have shown simulated power efficiencies greater than 150 Gflop/s/Watt (single precision) in 90nm processes for a range of signal processing and supercomputing applications. Such architectures depart from the traditional path of general purpose and DSP architectures in ways that are much more in tune with current VLSI physical issues, such as the importance of locality, degreees of parallelism, fine-grained memory, and in execution mechanisms; the term "streaming" has been adopted to describe and refer to them. The efficiency comes at a cost, however, in terms of the complexity of programming. We will discuss a software architecture for programming developed within the Morphware Forum, including the Streaming Virtual Machine, and the a high-level compiler, R-Stream, that Reservoir is developing within this software architecture, and show current results.
Biography: Richard A. Lethin, Directing Engineer (PI), received his B.S. in Electrical Engineering from Yale University in 1985 and M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from MIT in 1992 and 1997. Richard's graduate school education was sponsored by a fellowship from the John and Fannie Hertz Foundation, an organization committed to producing leaders in technology for national security. His M.S. thesis described the high-functionality logic simulator that was used to design and validate the MIT J-Machine, which is the largest working academic parallel computer (1024 custom nodes) ever constructed. Richard was one of the members of the core design team for the J-Machine's Message-Driven-Processor. Richard's Ph.D. thesis developed analytical queuing and simulation models to identify and characterize problems in the J-Machine's communications network design at heavy traffic loads, and to suggest and evaluate mechanisms to prevent them. Prior to MIT, Richard was one of the hardware developers of the Multiflow Trace VLIW, responsible for the floating-point section and personally responsible for the upgrades to the hardware design that became Multiflow's second-generation product. Subsequently, at Reservoir, and at MIT, Richard has retargeted and enhanced the Multiflow Trace Scheduling Compiler for several machines, including the MIT M-Machine. Richard joined Reservoir Labs in 1997 and became President in 1998, and under his leadership, the company has delivered R&D services and technologies in the areas of compilers and computer architecture with consistent customer satisfaction. Currently, Richard is working as PI of Reservoir^Os project developing a High Level Compiler as part of DARPA^Os Polymorphous Computer Architecture (PCA) program.