Due Date: September 8, 2003 at 3:00pm
Estimated Completion Time: 10 hrs.
This lab will introduce you, the student, to the Cadence Virtuoso IC layout tools and set the stage for future labs. You will first setup Cadence on your UNIX account. Then, you will run the Virtuoso Layout tutorial. After that, you will design and verify your own logic gates using MOSIS design rules.
The first step is to set up your UNIX account to allow you to use of the Cadence design package. The setup scripts have been designed to minimize the changes to your .cshrc file, so you don't have to carry around all of the path information for Cadence when you are not using it.
The following tutorials will teach you how to interact with the Cadence tools. Chapter 1 of the tutorial contains instructions on how to set up your account for usage with Cadence tools.
Purpose of Tutorials:
Chapter 1: How to setup your account and interact with the Cadence tools (contains questions to be handed in)
Chapter 2: Walk-through of INV cell design with DRC (useful for Section III. Part (iii.))
Chapter 3: Walk-through of MUX design using a hierarchy of NAND2 and INV cells
Chapter 4: Running the DRC for the MUX design
Once your account is setup to use Cadence tools, you may access help by typing in the following command at the terminal window.
use ncsu
cdsdoc
This brings up the browser window. To locate help for virtuoso, take the following links
Please answer the following questions using Cadence help.
What are the AV, NV, AS, and NS buttons of the LSW used for?
What is the keyboard shortcut to create a path?
How do you "flatten" the hierarchy of a cell and what is this procedure used for?
Open up the cell "tofix" in library "lab1".
Identify and correct all of the types of DRC errors. For each type of error, list the rule violated, one coordinate where the violation occurs, and what was done to correct the area. Please note that you should identify ALL the errors in the cell, even though multiple errors might be corrected by a single action.
Design the layout for the cells below using minimum sizing:
Double-sized (i.e. double-width) 4-input NAND gate.
2-input XNOR (assume the complements of the two inputs are available and do not to be generated by the XNOR circuit, itself)
f = a'bc’+a’b (’ denotes complementation) using only 2-input NOR gates and inverters. Please note that you should create this cell from scratch (i.e., NO hierarchical design and do NOT use any NOR and INV cells you have created). Although you will need to create multiples of the same types of gates, the wiring need not be identical. Therefore, there is more opportunity to minimize cell area (sharing active regions, for example) than if identical cell instances were copied in from a library.
In the layout, pins should be created on the Metal2.pn layer (for easier troubleshooting), with the input pins on the left side of the cell and the output pin on the right side. Also, the VDD and GND buses should run horizontally all the way across the top and bottom of the cell, respectively.
The layouts should be minimized for area.
Do not forget substrate and well contacts.
Also remember to size the transistors so that the cells have the same (and minimum) worst-case rise and fall times.
Sizing is important. The layout should be printed with the ruler. You will be graded on the area of your cell.
Provide a DRC report of cells without errors or warnings.
For color printouts, use printer HP308Color or HP309Color, use Display Type "display" in Plot Options, and fit the plot to the page.
In order to see what the DRC rules are, go to Verify-> DRC and check the "echo commands" box. This will echo all the DRC checks to the main window when DRC is run.
PRINTING!!! Printing is always an issue with this lab. Be sure to complete the lab with plenty of time (a day or two) left to print out layouts. You may have to contact help@ece.gatech.edu if printers go down (they may). Readability is important; if you cannot see to interpret a layout it will not be graded. Black and white layouts are unacceptable!
Running an Incremental DRC - The system keeps track of any changes you made since the last DRC. You can run an incremental DRC to check only your changes to the design. This makes the DRC go faster.
In the layout view, choose Verify -> DRC to display the DRC form.
Set “Checking Limit” to incremental.
Click OK to run DRC.
Printing the DRC report:
There is a log file produced (and overwritten) in your home directory called
CDS.log every time you run icfb. The way we prefer to print a DRC log file
is to start a new icfb session (make sure there are no previously running
sessions), run DRC (please uncheck the echo commands option), and then exit icfb.
You can then print this log file (or save it to a different filename). Edit out
any junk from your DRC report file.
Here is an example of what we expect to see for a "clean" DRC report.
To print to hp printer in room 309:
lpr -P hp309@cmpe-intel CDS.log
To print to hp printer in room 308:
lpr -P hp308@cmpe-intel CDS.log
About P-Island and N-Well:
Wherever there exists the p-island layer without an overlap of n-well, a
substrate connection is generated. With the exception of substrate contacts, all
p-islands should be completely surrounded by n-well. If the n-well layer cuts
through a contact, then it will short that contact to ground, and it may lead to
a DRC warning saying that GND and a net are shorted. Remember, there should be
no warnings or errors in a "clean" DRC report.