>Reading previous tests about the class, I met two terms I could not understand: 
"float" output and "short" output. What do they refer to in switch network?
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If we have two switches in series, with the output connected in the center and the positive and negative voltage supply line connected at either end:

    (-)----------o-/ o--------Output---------o/ o-------(+)

The Output is in the Float state when both switches are Open.

The output is in the Short state when both switches are closed.

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In CMOS logic, the Pull-up Network (of p-type FETs) and the Pull-down Network (of n-type FETs) can independently be "Open" or "Closed", in switch terminology.

The table below shows the Output State in terms of the Pull-up and Pull-down network states.

	Pull-up   		Pull-down 		Output

	Open      		Closed     		Logic zero (0 volts)

	Closed     		Open      		Logic one (Vdd volts)

	Open      		Open      		Float (no voltage applied)

	Closed     		Closed     		Short (from Vdd to Vss), "crowbar"

The first two cases are the only cases for a logic gate that represents a Boolean function.  If for any set of inputs the gate's output is Float or Short, we say that the gate can not be represented by a Boolean Function.  That's why the Pull-up network has to be a "Compliment" of the Pull-down network (if one is Open, the other is Closed).

The Short state is to be avoided, since it allows excessive current to float and might burn out a connection or switch.

Later we will study "Don't Care" states where, for example, we may know that inputs A and B+C will never be "1" simultaneously.  We thus don't care what the output is when (A,B,C) = (1,0,1), (1,1,0), or (1,1,1).  While it would be a bad design practice, we might simplify a gate design by letting the Output be a Float or Short for these input vectors.

Not needed for ECE2030:

Designers of clocked CMOS circuits may intentionally design a gate to go into the Float state for part of the clock cycle, to store the last output logic state (0 or 1) on the capacitance of the output connection and the gates of the next-stage FETs.  

John Copeland