As microprocessors continue to shrink to the beat of Moore's Law, the microprocessor industry has an ever-growing number of obstacles to overcome. No longer is a simple process shrink enough to guarantee the exponential performance improvement we've all come to expect. Designers must grapple with the memory wall, power consumption, δI/δt noise, and wire delay, just to name a few. One very promising solution is to design in the third dimension.
Three dimensional design is a very powerful technology. At its most basic, it allows for multiple layers of active silicon to be stacked on top of one another with very short and very dense die-to-die (d2d) vias connecting the logic. This reduces wire delay, which in turn decreases power consumption and increases operating frequency. For example, by stacking banks of L2 cache across two layers, we can halve the word- or bit-line wire-length. Since the charge time of a wire is RC, and both these values are linear with respect to the length of the wire, we've cut the charge time of these lines by a factor of four. Reducing the length also reduces the power consumed by driving the wire. Simultaneously reducing power and improving performance means everyone wins.
 Two layers of active silicon bonded face-to-face |
Of course, 3D technology is not limited to the stacking of high-performance processor modules. Heterogenous module stacking is another powerful possibility. Technologies that don't normally play well together (like high-performance CMOS and DRAM) can both be manufactured in their own dedicated and highly- optimized processing lines and then bonded together. This ensures both components are of the highest quality while still achieving very high integration. The news, however, is not all good (it never is). There are many interesting challenges facing academia and industry before 3D can realize its full potential. For example, CAD tools (particularly HDL synthesis) must be completely rewritten to accomodate multiple levels of silicon, and all components must be reexamined in order to fully utilize the potential of 3D (for more on this, please see the work of my fellow researcher, K. Puttaswamy). |
Another problem, and my particular interest in this field, is pre-bond testability of 3D layers. In a traditional planar design, each die comes off the manufacturing line complete, ready for automatic test equipment (ATE) to apply the test patterns and verify proper execution. In a 3D process, each die comes of the line incomplete and must be bonded to its fellows before it will function properly. Of course, you can wait on testing until the final chip is assembled (called bond-and-pray, and its the state-of-the-art right now). The problem is, any single bad layer in the stack will result in the failure of the entire stack. Thus, whatever the inherent yield of your process, it gets multiplied with each untested layer that is bonded. Assuming a process with 90% yield per layer, a two-layer chip will have a final yield of 81%, a four-layer chip 66%, and we can just forget about chips with tens of layers. Therefore, we need to be able to test these designs before the layers are bonded together.
So exactly how can we test these layers before bonding has occurred? That is the focus of my current work.
My research is presently focused on the design of a base case for pre-bond testability. In this base case, I assume a 3D floorplan comprised of planar modules, as shown below.
A 3D floorplan comprised of planar modules.
Module size and functionality is based on the microarchitecture of the Alpha 21264.
By assuming planar modules, we can readily apply many of the test methodologies already developed for planar designs. For example, rather than viewing each layer as partial processor, we can view it as a perfectly isolated scan island. Existing scan techniques can be utilized for testing most of the layer. The only things we need to provide are a method for injecting values onto buses coming from other layers and a method for sampling values on buses going to other layers. This is easier said than done as we must carefully consider performance and area impacts. Protecting performance means minimizing the load introduced on critical paths path the injection and sampling hardware. Conserving area means minimizing the area required to provide value injection and sampling. Of these two, area is likely the greater problem, as inter-layer buses can be thousands of bits wide. Can we afford a dedicated scan-flop for each of these lines? If not, what tricks will we need to play? Answering these questions is the main thrust of my current work.
| Assuming the necessary circuity can be designed to provide injection and sampling of test data, there are secondary concerns that must be addresses. Primary here is the question of how to actually interface each layer to the ATE. I assume a standard approach using test probes touching down and providing the necessary signals. But how does touch down occur? We could potentially touch down on the backside of each layer (as shown in diagram A). However, this would require first thinning the wafer, making it extremely brittle and likely to break under the pressure of touch down. I favor faceside test (as shown in diagram B). It can be performed by current testing equipment using standard methodologies, avoiding the concerns of backside test. However, it has its own problem. First, the test pads - where the test probes touch down - must compete for space with the dense d2d vias, which are an order of magnitude smaller. This problem can be easily overcome by relegating the test pads to via-sparse areas of the layer face, but only if such areas exist. Second, after bonding has occured, the test pads will simply sit there, unutilized, for the rest of the chip's lifetime. Therefore, they must either be isolated from the critical paths or put to use some other way. For example, a test pad that provides access to a layer's clock tree must be isolated, as the load it represents would be devestating to the precisely designed tree. On the other hand, test pads tied to the power and ground networks may naturally serve as decoupling capacitors (decap), in which case we should try to place them nearer high-activity modules. Such questions must be addressed before a test solution can be fully realized. |
 Two options for location of test pads: (a) backside and (b) faceside |
Here's a short list of acronyms commonly used in the fields of 3D integration and test, provided for your convenience.
- ATE - automated testing equipment. These systems apply test vectors to the DUT and check the outputs
- CAD - computer-aided design
- CUT - circuit under test
- d2d - die-to-die, as in a die-to-die via
- decap - decoupling capacitor. These capacitors are used to diminish variation in the power supply voltage caused by sudden, massive current draw (for example, on the clock edge when all synchronous elements switch simultaneously).
- DUT - device under test
- HDL - hardware description language. HDLs allow an engineer to design the hardware of a system in software