Simulating with bitstreams

There are many tools on the 'Tech network which let you make piece-wise linear (pwl) bit streams for simulation purposes; however, none of them seem to work. They were all missing some sort of library or what not. Therefore, I've written my own.

pwlbits

The program, which I named "pwlbits", resides in ~degs/tools/pwlbits.class (source code).

::app screenshot::

Figure 1. The pwlbits application running. Don't mind the font warnings.

Non-obvious behavior occurs in the following fields:

bitstream: the values will be clocked in from left to right.
rising/falling: the clock edge mid-data.
save: 2 files are created, bitstream and clock

The program makes a clock waveform which rises or falls at the 1/2 way point of the data stream; therefore there are two files created, <something>.pwl and <something>.clk. The .pwl file is the bit stream, and the .clk file is the accompanying clock stream. The files can then be assigned to "vpwlf" voltage-sources from analogLib.

Figure 2. An example schematic which uses "vpwlf" from analogLib for the shift register clock and data sources.

Simulation Results

Graph of the clock and bitstream.