LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.all;

ENTITY clkdiv IS
	PORT(
		clk,reset								: IN	STD_LOGIC;
		clk_800k, clk_200k, clk_100				: OUT	STD_LOGIC);
END clkdiv;

ARCHITECTURE a OF clkdiv IS
	SIGNAL ClkDivisor_800k						: STD_LOGIC_VECTOR(6 DOWNTO 0);	--Clk divisor 25Mhz/31~= 800KHz
	SIGNAL ClkDivisor_100						: STD_LOGIC_VECTOR(14 DOWNTO 0);	--Clk divisor 25Mhz/31~= 800KHz

BEGIN

	
	PROCESS (clk,reset)
	BEGIN
		if(reset = '0') then
			ClkDivisor_800k	<= "0000000";
			ClkDivisor_100 <= "000000000000000";
			clk_800k <= '0';
			clk_200k <= '0';
			clk_100 <= '1';
		ELSIF(clk'event AND clk = '1')then
			if(ClkDivisor_100 = "110000110100111") then
				ClkDivisor_100 <= "000000000000000";
				clk_100 <= '1';
				ClkDivisor_800k	<= "0000000";

				clk_800k <= '0';
				clk_200k <= '0';
			elsif(clkDivisor_800k = "0011111") then
				clk_800k <= '1';
				clk_200k <= '0';
				clkDivisor_800k <= clkDivisor_800k + 1;

				clk_100 <= '0';
				ClkDivisor_100 <= ClkDivisor_100 + 1;
			elsif(clkDivisor_800k = "0111110") then
				clk_800k <= '1';
				clk_200k <= '0';
				clkDivisor_800k <= clkDivisor_800k + 1;

				clk_100 <= '0';
				ClkDivisor_100 <= ClkDivisor_100 + 1;
			elsif(clkDivisor_800k = "1011100") then
				clk_800k <= '1';
				clk_200k <= '0';
				clkDivisor_800k <= clkDivisor_800k + 1;

				clk_100 <= '0';
				ClkDivisor_100 <= ClkDivisor_100 + 1;
			elsif(clkDivisor_800k = "1111011") then
				clk_800k <= '1';
				clk_200k <= '1';
				ClkDivisor_800k <= "0000000";

				clk_100 <= '0';
				ClkDivisor_100 <= ClkDivisor_100 + 1;
			else
				clk_800k <= '0';
				clk_200k <= '0';
				clkDivisor_800k <= clkDivisor_800k + 1;

				clk_100 <= '0';
				ClkDivisor_100 <= ClkDivisor_100 + 1;
			end if;
		END IF;
	END PROCESS;
END a;