LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.all;

ENTITY tester2 IS
	PORT(
		clk								: IN	STD_LOGIC;
		data							: OUT	STD_LOGIC;
		StartDecode						: OUT	STD_LOGIC);
END tester2 ;


ARCHITECTURE a OF tester2 IS
	SIGNAL ByteData				: STD_LOGIC_VECTOR(24 DOWNTO 0);				--ByteData
	SIGNAL State				: STD_LOGIC_VECTOR(1 DOWNTO 0);
	SIGNAL Pause				: STD_LOGIC_VECTOR(9 DOWNTO 0);
	SIGNAL Initialize			: STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN
	PROCESS (clk)
	BEGIN		
		IF(clk'event AND clk = '1')THEN 
			IF(Pause = "0000000000") THEN										--Pause (init)
				CASE state IS
					WHEN "00" =>
						IF(ByteData = "0000000000000000000000000") THEN						--ByteData
							Data <= '1';	
						ELSE
							Data <= '0';
						END IF;
						State <= "01";
					WHEN "11" =>
						Data <= '1';
						State <= "00";
						ByteData <= ByteData(23 DOWNTO 0) & '0';			--ByteData(X-1 downto 0)
					WHEN OTHERS =>	
						IF(ByteData = "0000000000000000000000000") THEN		--ByteData
							Pause <= "1111111111";							--Pause (Fin)
							Data <= '1';
							State <= "00";
							IF NOT(Initialize = "111") THEN				
								Initialize <= Initialize + 1;
							END IF;
						ELSE
							IF(ByteData(24) = '0') THEN						--ByteData(X)
								Data <= '0';
							ELSE
								Data <= '1';
							END IF;
							State <= State + 1;
						END IF;
				END CASE;		
				StartDecode <= '0';
			ELSE
				StartDecode <= '1';
				Pause <= Pause - 1;
			 	Data <= '1';
				IF(Initialize = "111") THEN
					ByteData <= "0100000000000011000000001";
				ELSE
					ByteData <= "0000000010000000000000000";  --010000000000001100000000	--ByteData
				END IF;
			END IF;

		END IF; --IF(reset = '0') THEN
	END PROCESS; --process
END a;  --behavior