LCD Display

The Hardware

The interface to the LCD display is fairly straight forward:

ISA Bus - Altera FPGA - Connection Board - LCD interface

The ISA bus is brought out to the Altera board with a ribbon cable. The Altera FPGA is programmed to listen to address 0x3E0 for data and 0x3E1 for commands (toggle control lines, etc). 10 data lines are then driven by the FPGA depending on the data sent to it over the ISA bus. Power and ground are also drawn from the Altera board.

The VHDL code on the FPGA is a simple I/O port with two addresses. The first address is where 8 data bits are to be written. The second address only uses the first two bits. These bits correspond to the E (enable) and RS (register select). All data is sent to the lower address and then the E line on the second address is clocked high then low. If the RS line is high, the LCD display treats the information as data. If it's low, it is treated as a special instruction for the display (home, clear screen, etc).

The connection board simply adds a potentiometer for controlling the contrast of the LCD display. The connection board rearranges a few of the signals and sends them on to the display over the 14-pin cable. 8 data lines, one enable, one control/data line, power, and ground are the lines used by the display.

The display itself is a Hitachi 21210 20x1 display.