--
-- ****************************************
-- top_dlx
-- contains : everything!
-- ****************************************
--
LIBRARY SYNOPSYS, IEEE;
USE SYNOPSYS.attributes.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_signed.ALL;
ENTITY TOP_DLX IS
PORT(
PC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reset : IN STD_LOGIC;
phi2 : IN STD_LOGIC
);
END TOP_DLX;
ARCHITECTURE behavioral OF TOP_DLX IS
COMPONENT IFETCH
PORT(
LInstruction : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Instout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
do_Branch : IN STD_LOGIC;
phi2 : IN STD_LOGIC;
reset : IN STD_LOGIC;
PCout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
LPCAdd : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LNewPC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Stallvect : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT EXECUTE
PORT(
Lrr1d_bus : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Lrr2d_bus : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LLrr2d_bus : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Lextend : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Lwra_bus : IN STD_LOGIC_VECTOR( 4 DOWNTO 0);
LLwra_bus : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0);
LALUOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
SysCont : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
LSysCont : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
LZero : IN STD_LOGIC;
LEql : IN STD_LOGIC;
reset : IN STD_LOGIC;
phi2 : IN STD_LOGIC;
Lmux_out : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Lra_bus_out : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LLInstruction : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LLLInstruction : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Hazardvect
Hazardvect : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
Stallvect : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
ForceMuxVect : IN STD_LOGIC_VECTOR( 3 DOWNTO 0)
);
END COMPONENT;
COMPONENT IDECODE
PORT(
LInstruction : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Lrr1d_bus : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Lrr2d_bus : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
RegWrite : IN STD_LOGIC;
LExtend : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-- phi1 : in std_logic;
phi2 : IN STD_LOGIC;
reset : IN STD_LOGIC;
Lwra_bus : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
Lwra2_bus : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
PCadd : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LPCadd : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
LZero : OUT STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
wrd_bus : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Lrr1a_bus : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
Lrr2a_bus : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
-- BEQ/BNE
Leql : OUT STD_LOGIC;
LLInstruction : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Stallvect : IN STD_LOGIC_VECTOR( 3 DOWNTO 0)
);
END COMPONENT;
COMPONENT DMEMORY
PORT(
rd_bus : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
LALUOut : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LLrr2d_bus : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
MemRead : IN STD_LOGIC;
Memwrite : IN STD_LOGIC;
MemtoReg : IN STD_LOGIC;
-- phi1 : in std_logic;
phi2 : IN STD_LOGIC;
reset : IN STD_LOGIC;
LLwra_bus : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
LLLwra_bus : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
LSysCont : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LLSysCont : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
Lmux_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Lra_bus_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
LLLInstruction : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LLLLInstruction : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Hazardvect : IN STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
COMPONENT HAZARD
PORT(
Instruction : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LInstruction : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LLInstruction : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LLLInstruction : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LLLLInstruction : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- phi1 : in std_logic;
phi2 : IN STD_LOGIC;
reset : IN STD_LOGIC;
Hazardvect : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
Stallvect : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
ForceMuxVect : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0)
);
END COMPONENT;
-- put signals here
-- 8bit
SIGNAL Instru12 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL PC12 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL LPCAdd31 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rr1d23 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rr2d23 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL lrr2d34 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL extend23 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wra_bus23 : STD_LOGIC_VECTOR( 4 DOWNTO 0);
SIGNAL lwra_bus34 : STD_LOGIC_VECTOR( 4 DOWNTO 0);
-- signal lop23 : std_logic_vector( 5 downto 0);
-- signal lopx23 : std_logic_vector( 5 downto 0);
SIGNAL llwra_bus42 : STD_LOGIC_VECTOR( 4 DOWNTO 0);
SIGNAL aluout34 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rdbus52 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SysCont34 : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- do_branch
SIGNAL SysCont3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SysCont45 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL lzero23 : STD_LOGIC;
SIGNAL LEql23 : STD_LOGIC;
-- junk signals (use for haz detect)
SIGNAL lwra2_bus : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL lrr1a_bus : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL lrr2a_bus : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- junk for (hazards) (jat)
SIGNAL lmuxout53 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL lrabusout53 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- BNE/BEQ
SIGNAL Leql : STD_LOGIC;
SIGNAL Instru23 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Instru34 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Instru45 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Hazardvect : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL Stallvect : STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL ForceMuxVect : STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL Instout : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
IFETCH1: IFETCH
PORT MAP(
LInstruction => Instru12,
Instout => Instout,
do_Branch => SysCont3(1),
-- phi1 => phi1,
phi2 => phi2,
reset => reset,
PCout => PC,
LPCAdd => LPCAdd31,
LNewPC => PC12,
Stallvect => Stallvect
);
EXECUTE1: EXECUTE
PORT MAP(
Lrr1d_bus => rr1d23,
Lrr2d_bus => rr2d23,
LLrr2d_bus => lrr2d34,
Lextend => extend23,
Lwra_bus => wra_bus23,
LLwra_bus => lwra_bus34,
-- Lop => lop23,
-- Lopx => lopx23,
LALUOut => aluout34,
SysCont => SysCont3,
LSysCont => SysCont34,
LZero => lzero23,
LEql => LEql23,
reset => reset,
-- phi1 => phi1,
phi2 => phi2,
Lmux_out => lmuxout53,
Lra_bus_out => lrabusout53,
LLInstruction => Instru23,
LLLInstruction => Instru34,
Hazardvect => Hazardvect,
Stallvect => Stallvect,
ForceMuxVect => ForceMuxVect
);
IDECODE1: IDECODE
PORT MAP(
LInstruction => Instru12,
Lrr1d_bus => rr1d23,
Lrr2d_bus => rr2d23,
RegWrite => SysCont45(0),
LExtend => extend23,
-- phi1 => phi1,
phi2 => phi2,
reset => reset,
Lwra_bus => wra_bus23,
-- haz sig
Lwra2_bus => lwra2_bus,
PCadd => PC12,
LPCadd => LPCAdd31,
LZero => lzero23,
wraddress => llwra_bus42,
wrd_bus => rdbus52,
-- haz sig
Lrr1a_bus => lrr1a_bus,
-- haz sig
Lrr2a_bus => lrr2a_bus,
-- Lop => lop23,
-- Lopx => lopx23,
-- BEQ/BNE
Leql => Leql23,
LLInstruction => Instru23,
Stallvect => Stallvect
);
DMEMORY1: DMEMORY
PORT MAP(
rd_bus => rdbus52,
LALUOut => aluout34,
LLrr2d_bus => lrr2d34,
MemRead => SysCont45(3),
Memwrite => SysCont34(2),
MemtoReg => SysCont45(4),
-- phi1 => phi1,
phi2 => phi2,
reset => reset,
LLwra_bus => lwra_bus34,
LLLwra_bus => llwra_bus42,
LSysCont => SysCont34,
LLSysCont => SysCont45,
Lmux_out => lmuxout53,
Lra_bus_out => lrabusout53,
LLLInstruction => Instru34,
LLLLInstruction => Instru45,
Hazardvect => Hazardvect
);
HAZARD1: HAZARD
PORT MAP(
Instruction => Instout,
LInstruction => Instru12,
LLInstruction => Instru23,
LLLInstruction => Instru34,
LLLLInstruction => Instru45,
-- phi1 => phi1,
phi2 => phi2,
reset => reset,
Hazardvect => Hazardvect,
Stallvect => Stallvect,
ForceMuxVect => ForceMuxVect
);
-- ***************************************************************
-- dobra31 <= SysCont(6);
-- ***************************************************************
END behavioral;
CONFIGURATION DLX1 OF TOP_DLX IS
FOR behavioral
FOR IFETCH1: IFETCH
USE ENTITY WORK.IFETCH(behavioral);
END FOR;
FOR EXECUTE1: EXECUTE
USE ENTITY WORK.EXECUTE(behavioral);
END FOR;
FOR IDECODE1: IDECODE
USE ENTITY WORK.IDECODE(behavioral);
END FOR;
FOR DMEMORY1: DMEMORY
USE ENTITY WORK.DMEMORY(behavioral);
END FOR;
FOR HAZARD1: HAZARD
USE ENTITY WORK.HAZARD(behavioral);
END FOR;
END FOR;
END DLX1;