1 Tutorial I: The 15 Minute Design 2
1.1 Design Entry using the Graphic Editor 6
1.2 Compiling the Design 9
1.3 Simulation of the Design 10
1.4 Downloading Your Design to the UP 1 Board 12
1.5 The 10 Minute VHDL Entry Tutorial 14
1.6 Compiling the VHDL Design 17
1.7 The 10 Minute Verilog Entry Tutorial 17
1.8 Compiling the Verilog Design 21
1.9 Timing Analysis 22
1.10 The Floorplan Editor 23
1.11 Symbols and Hierarchy 24
1.12 Functional Simulation 24
1.13 For additional information 24
1.14 Laboratory Exercises 25

2 The Altera UP 1 CPLD Board 30
2.1 Programming Jumpers 31
2.2 MAX 7000 Device and UP 1 I/O Features 31
2.3 MAX and FLEX Seven-segment LED Displays 31
2.4 FLEX 10K Device and UP 1 I/O Features 34
2.5 Obtaining a UP 1 Board and Power Supply 36

3 Programmable Logic Technology 38
3.1 CPLDs and FPGAs 40
3.2 Altera MAX 7000S Architecture – A Product Term CPLD Device 41
3.3 Altera FLEX 10K Architecture – A Look-Up Table CPLD Device 42
3.4 Xilinx 4000 Architecture – A Look-Up Table FPGA Device 46
3.5 Computer Aided Design Tools for Programmable Logic 48
3.6 Applications of FPLDs 48
3.7 For Additional Information 49
3.8 Laboratory Exercises 49

4 Tutorial II: Sequential Design and Hierarchy 52
4.1 Install the Tutorial Files and UP1core Library 52
4.2 Open the Tutor2 Schematic 52
4.3 Browse the Hierarchy 54
4.4 Using Buses in a Schematic 55
4.5 Testing the Pushbutton Counter and Displays 56
4.6 Testing the Initial Design on the UP 1 Board. 57
4.7 Fixing the Switch Contact Bounce Problem 58
4.8 Testing the Modified Design on the UP 1 Board. 59
4.9 Laboratory Exercises 59

5 UP1core Library Functions 64
5.1 UP1core DEC-7SEG: Hex to Seven-segment Decoder 65
5.2 UP1core Debounce: Pushbutton Debounce 66
5.3 UP1core OnePulse: Pushbutton Single Pulse 67
5.4 UP1core Clk_Div: Clock Divider 68
5.5 UP1core VGA_Sync: VGA Video Sync Generation 69
5.6 UP1core CHAR_ROM: Character Generation ROM 71
5.7 UP1core Keyboard: Read Keyboard Scan Code 72
5.8 UP1core Mouse: Mouse Cursor 73

6 Using VHDL for Synthesis of Digital Hardware 76
6.1 VHDL Data Types 76
6.2 VHDL Operators 77
6.3 VHDL Based Synthesis of Digital Hardware 78
6.4 VHDL Synthesis Models of Gate Networks 78
6.5 VHDL Synthesis Model of a Seven-segment LED Decoder 79
6.6 VHDL Synthesis Model of a Multiplexer 81
6.7 VHDL Synthesis Model of Tri-State Output 82
6.8 VHDL Synthesis Models of Flip-flops and Registers 82
6.9 Accidental Synthesis of Inferred Latches 84
6.10 VHDL Synthesis Model of a Counter 84
6.11 VHDL Synthesis Model of a State Machine 85
6.12 VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter 87
6.13 VHDL Synthesis of Multiply and Divide Hardware 88
6.14 VHDL Synthesis Models for Memory 89
6.15 Hierarchy in VHDL Synthesis Models 92
6.16 Using a Testbench for Verification 94
6.17 For Additional Information 95
6.18 Laboratory Exercises 95

7 State Machine Design: The Electric Train Controller 100
7.1 The Train Control Problem 100
7.2 Track Power (T1, T2, T3, and T4) 102
7.3 Track Direction (DA1 - DA0, and DB1 - DB0) 102
7.4 Switch Direction (SW1, SW2, and SW3) 103
7.5 Train Sensor Input Signals (S1, S2, S3, S4, and S5) 103
7.6 An Example Controller Design 104
7.7 VHDL Based Example Controller Design 108
7.8 Simulation Vector File for State Machine Simulation 110
7.9 Running the Train Control Simulation 113
7.10 Running the Video Train System (After Successful Simulation) 114
7.11 Laboratory Exercises 115

8 A Simple Computer Design: The uP 1 120
8.1 Computer Programs and Instructions 121
8.2 The Processor Fetch, Decode and Execute Cycle 122
8.3 VHDL Model of the uP 1 126
8.4 Simulation of the uP 1 Computer 129
8.5 Laboratory Exercises 130

9 VGA Video Display Generation 134
9.1 Video Display Technology 134
9.2 Video Refresh 134
9.3 Using a CPLD for VGA Video Signal Generation 137
9.4 A VHDL Sync Generation Example: UP1core VGA_SYNC 138
9.5 Final Output Register for Video Signals 140
9.6 Required Pin Assignments for Video Output 140
9.7 Video Examples 141
9.8 A Character Based Video Design 141
9.9 Character Selection and Fonts 142
9.10 VHDL Character Display Design Examples 145
9.11 A Graphics memory design example 147
9.12 Video Data Compression 148
9.13 Video Color Mixing using Dithering 149
9.14 VHDL Graphics Display Design Example 149
9.15 Laboratory Exercises 151

10 Communications: Interfacing to the PS/2 Keyboard 154
10.1 PS/2 Port Connections 154
10.2 Keyboard Scan Codes 155
10.3 Make and Break Codes 155
10.4 The PS/2 Serial Data Transmission Protocol 155
10.5 Scan Code Set 2 for the PS/2 Keyboard 158
10.6 The Keyboard UP1core 160
10.7 A design example using the Keyboard UP1core 163
10.8 For additional information 164
10.9 Laboratory Exercises 164

11 Communications: Interfacing to the PS/2 Mouse 166
11.1 The Mouse UP1core 168
11.2 Mouse Initialization 168
11.3 Mouse Data Packet Processing 169
11.4 An example design using the Mouse UP1core 170
11.5 For additional information 170
11.6 Laboratory Exercises 170

12.1 The UP1-bot Design 172
12.2 UP1-bot Servo Drive Motors 172
12.3 Modifying the Servos to make Drive Motors 173
12.4 VHDL Servo Driver Code for the UP1-bot 174
12.5 Sensors for the UP1-bot 176
12.6 Assembly of the UP1-bot Body 181
12.7 UP1-bot FLEX Expansion B Header Pins 188
12.8 For Additional Information 189
12.9 Laboratory Exercises 190

13 A RISC Design: Synthesis of the MIPS Processor Core 196
13.1 The MIPS Instruction Set and Processor 196
13.2 Using VHDL to Synthesize the MIPS Processor Core 199
13.3 The Top Level Module 200
13.4 The Control Unit 203
13.5 The Instruction Fetch Stage 205
13.6 The Decode Stage 208
13.7 The Execute Stage 210
13.8 The Data Memory Stage 212
13.9 Simulation of the MIPS Design 213
13.10 MIPS Hardware Implementation on the UP 1 Board 214
13.11 For Additional Information 215
13.12 Laboratory Exercises 216

Appendix A: Generation of Pseudo Random Binary Sequences 221
Appendix B: MAX+PLUS II Design and Data File Extensions 223
Appendix C: UP 1 Pin Assignments 225
Glossary 228
Index 237
About the Accompanying CD-ROM 240

PREFACE

Intended Audience

This text is intended to provide an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic. There are a number of excellent texts on digital logic design. For the most part, these texts do not include or fully integrate modern CAD tools, logic simulation, logic synthesis using hardware description languages, design hierarchy, and current generation field programmable logic device (FPLD) technology. The goal of this text is to introduce these topics in the laboratory portion of the course.
Design engineers working in industry may also want to consider this text for a rapid introduction to FPLD technology and logic synthesis using commercial CAD tools, if they have not had previous experience with this new and rapidly evolving technology.

Two tutorials on the Altera CAD tool environment, an overview of programmable logic, and a design library with several easy to use input and output functions were developed for this text to help students get started quickly. Early design examples use schematic capture and library components. VHDL is used for more complex designs after a short introduction to VHDL based synthesis.

The approach used in the text more accurately reflects contemporary practice in industry than the more traditional TTL protoboard based laboratory courses. The use of rapid prototyping with a hardware description language (HDL) and logic synthesis makes current SSI and MSI TTL based laboratory projects trivial. With modern logic synthesis tools and large FPLDs, more advanced designs are needed to present challenging laboratory projects. Rather than being limited to a few TTL chips that will fit on a small protoboard, designs containing tens of thousands of gates are possible even with student versions of the CAD tools and the UP 1 board. Even student laboratory projects can now implement entire digital systems.

Over the past year, we have developed a number of interesting and challenging laboratory projects involving serial communications, state machines with video output, video games and graphics, simple computers, keyboard and mouse interfaces, robotics, and pipelined RISC processor cores.

These projects were all developed on the student version of the Altera CAD tools and can be implemented on the Altera UP 1 board. Source files and additional example files are available on the CDROM for all designs presented in the text. These design files can also be used as case studies. The student version of the PC based CAD tool on the CDROM can be freely distributed to students. Students can purchase their own UP 1 board for little more than the price of a contemporary textbook. As an alternative, a few of the low-cost UP 1 boards can be shared among students in a laboratory. Course instructors should contact the Altera University Program for detailed information on obtaining student versions of the CAD tools and UP 1 boards for student laboratories.

Topic Selection and Organization

Chapter 1 is a short CAD tool tutorial that covers design entry, simulation, and hardware implementation using an FPLD. The majority of students can enter the design, simulate, and have the design successfully running on the UP 1 board in less than thirty minutes. After working through the tutorial and becoming familiar with the process, similar designs can be accomplished in less than 10 minutes.

Chapter 2 provides an overview of the UP 1 FPLD development board. The features of the board are briefly described. Several tables listing pin connections of various I/O devices serve as an essential reference whenever a hardware design is implemented on the UP 1 board.

Chapter 3 is an introduction to programmable logic technology. The capabilities and internal architectures of the most popular CPLDs and FPGAs are described. These include the MAX 7000 and FLEX 10K family CPLDs used on the UP 1 board, and the Xilinx 4000 family FPGAs. This information is not found in current digital logic textbooks.

Chapter 4 is a short CAD tool tutorial that serves as both a hierarchical and sequential design example. A counter is clocked by a pushbutton and the output is displayed in the seven-segment LED’s. The design is downloaded to the UP 1 board and some real world timing issues arising with switch contact bounce are resolved. It uses several functions from the UP1core library which greatly simplify use of the UP 1’s input and output capabilities.

Chapter 5 describes the available UP1core library I/O functions. The I/O devices include switches, seven-segment LED’s, a multiple output clock divider, VGA output, keyboard input, and mouse input.

Chapter 6 is an introduction to the use of VHDL for the synthesis of digital hardware. Rather than a lengthy description of syntax details, models of the commonly used digital hardware devices are developed and presented. Most VHDL textbooks use models developed for simulation only and they frequently use language features not supported in synthesis tools. Our easy to understand synthesis examples were developed and tested using the Altera VHDL CAD tools.

Chapter 7 is a state machine design example. The state machine controls a virtual electric train system simulation with video output generated directly by the CPLD. Using track sensor input, students must control two trains and three track switches to avoid collisions.

Chapter 8 develops a model of a simple computer. The fetch, decode, and execute cycle is introduced and a brief model of the computer is developed using VHDL. A short assembly language program can be entered in the FPLD’s internal memory and executed in the simulator.

Chapter 9 describes how to design an FPLD-based digital system to output VGA video. Numerous design examples are presented containing video with both text and graphics. Fundamental design issues in writing simple video games and graphics using the UP 1 board are examined.

Chapter 10 describes the PS/2 keyboard operation and presents interface examples for integration in designs on the UP 1 board. Keyboard scan code tables, commands, status codes, and the serial communications protocol are included. VHDL code for a keyboard interface is also presented.

Chapter 11 describes the PS/2 mouse operation and presents interface examples for integration in designs on the UP 1 board. Commands, data packet formats, and PS/2 serial communications protocols are included.

Chapter 12 develops a design for an adaptable mobile robot using the UP 1 board. Servo motors and several sensor technologies for a low cost mobile robot are described. A sample servo driver design is presented. Commercially available parts to construct the robot described in Chapter 12 can be obtained for around $50. Several robots can be built for use in the laboratory. Students with their own UP 1 board may choose to build their own robot following the detailed instructions found in section 12.6.

Chapter 13 describes a single clock cycle model of the MIPS RISC processor based on the hardware implementation presented in the widely used Patterson and Hennessy textbook, Computer Organization and Design The Hardware/Software Interface. Laboratory exercises that add new instructions, features, and pipelining are included at the end of the chapter.

Laboratory problems and a variety of design projects are included at the end of each chapter. A number of design projects and options are presented so that these projects can change in future offerings of the course and fit into either semester or quarter systems.

We anticipate that many schools will still choose to begin with TTL designs on a small protoboard for the first few labs. The first chapter can also be started at this time since only an OR and a NOT logic function are used to introduce the CAD tool environment. The CAD tool can also be used for simulation of TTL labs, since an extensive TTL parts library is included with the student version.

Even though VHDL is a complex language, we have found after several years of experimentation that students can write VHDL to synthesize hardware designs after a short overview with a few basic hardware design examples. The use of VHDL templates and online help files in the CAD tool makes this process easier. After the initial experience with VHDL synthesis, students dislike the use of schematic capture on larger designs since it can be very time consuming. Experience in industry has been much the same since huge productivity gains have been achieved using HDL based synthesis tools for application specific integrated circuits (ASICs) and FPLDs.
Most digital logic classes include a simple computer design such as the one presented in Chapter 8 or a RISC processor such as the one presented in Chapter 13. If this is not covered in the first digital logic course, it could be used as a lab component for a subsequent computer architecture class.

A typical quarter or semester length course could not cover all of the topics presented. The material presented in Chapters 7 through 13 can be used on a selective basis. The keyboard and mouse are supported by UP1core library functions, and the material presented in Chapters 10 and 11 is not required to use these library functions for keyboard or mouse input. It is included for those who choose to write their own keyboard or mouse interfaces, and it also makes an interesting case study in serial communications. Information on video generation, PS/2 keyboard, and mouse interfacing is not readily available elsewhere.

A video game based on the material in Chapter 9 can serve as the basis for a team design project. In one offering of the laboratory, students worked in design teams for three weeks on a video game. In the second offering of the laboratory, a robotics team design competition was held using ten of the robots in Chapter 12 equipped with IR proximity sensors. The IR sensors were used to detect and avoid obstacles. Our students really enjoyed working with the robot described in Chapter 12, and it presents almost infinite possibilities for an exciting design competition.

Software and Hardware Packages
The new student version of Altera’s MAX+PLUS II CAD tool is included with this book and the UP 1 Board is available from Altera at special student pricing. A board can be shared among several students in a lab, or some students may wish to purchase their own board. Students that have a home PC will want to seriously consider this option. Details and suggestions for additional cables and power supplies that may be required for a laboratory setup can be found in Section 2.5. Source files for all designs presented in the text are available on the CDROM.