Current Research

Placement for 3D integrated circuits under the following considerations:
  • Impact of Through-Silicon Via (TSV) on layout
  • Impact of TSV and Shallow-Trench Isolation (STI) stresses on carrier mobility
  • Temperature inside chip stacks
  • Supply voltage drop in power distribution network (PDN)

Previous Research

Thermal-aware clock-tree optimization

Research Interest

VLSI design, Computer architecture, and Embedded system.