Here's a snapshot of a system employing Tomasulo's dynamic scheduling.

• Null (empty) values are denoted by "-"
• If all operands are available, an instruction can issue and begin execution on the same cycle.
• When a reservation station obtains its last operand value, it can begin execution on the next cycle.
• Each pipelined execution unit has two reservation stations and can begin a new instruction every clock cycle.
• The execution unit latencies are FPAdd = 5, FPMult = 3, FPLoad/Store = 2. These latencies do not include writing the results to reservation stations and/or registers.
• Reservation stations are deallocated during the result writing cycle and can be reassigned on the following cycle. Deallocated but not reassigned reservation stations should be indicated with null fields.
• Initial register contents of R1: 100.

Instruction Status:

Reservation Stations:

Load/Store Buffers:

Register File Status

4a) [5 points] Suppose that instruction 1 issued in cycle C0. Which instructions will issue in the next 6 cycles (C1- C6)? For those instructions that cannot issue, briefly explain why they cannot.

4b) [10 points] Show the state of the system at the end of cycle 6 (C6).

Instruction Status:

Reservation Stations:

Load/Store Buffers:

Register File Status

4c) [5 points] Check the box below each instruction that wrote its results back to the register file during cycles C0-C6.

4d) [5 points] Check the box below each instruction that broadcasted its results on the Common Data Bus during cycles C0-C6.