Parallelization
Parallelism Estimation:
Retargeting existing code assets to parallel hardware execution
mechanisms is difficult, but can provide significant increases in
efficiency. We are developing techniques for estimating potential
parallelism in sequential code and the types (thread-level,
instruction-level, and data-parallel) that are inherent in a given
sequential program.
Extracting data parallelism:
With the advent of data parallel multimedia extensions to instruction
sets (e.g., MMX) and new massively parallel architectures, the
potential to efficiently exploit data parallelism in image and video
processing software is emerging. However the artifacts imposed by the
sequential programming languages in which they are written (e.g.,
loops, pointer variables, linear address spaces) can obscure the
parallelism and prohibit generation of efficient parallel code. We
are developing reengineering techniques for exposing the inherent data
parallelism in these applications to fuel a new generation of high
performance, high efficiency embedded processing systems. Software
understanding techniques are being developed to detect both the data
parallel operations and the underlying data structures hidden in the
code.
Parallelization Publications
Retargeting
Retargetable data parallel compilation:
The rapid development of embedded multimedia products will lead to a
diverse range of data parallel processing
platforms. High-computational demand applications (e.g., real-time
mpeg encoding) will drive specialized highly data parallel processors.
Low-computational demand applications will continue to exploit current
subword parallel instruction set extensions. The goal of this
research activity is to develop a compiler that can translate a single
application specification to any processor granularity along this
diverse architectural spectrum. The particular challenge is to allow
algorithms to be specified without architecture-dependent commitments
to grain size.
Distributed register file retargeting:
Traditional processors are designed with a single central register
file which has several drawbacks in terms of required die area, access
time, and power consumption. High levels of parallelism dictate a
large register file with a large number of registers and a large
number of access ports per register. A distributed register file
architecture can be used to alleviate this problem for new parallel
architectures. We are developing a code retargeting framework to
transform assembly-level code written in the traditional central
register file style to an explicitly distributed register file
architecture.
Memory usage transformations for efficient data movement:
We are combining application retargeting techniques with area- and
power-efficiency models to develop support for finding optimal on-chip
storage configurations. We have developed an automated retargeting
technique that is used in analyzing the storage requirements of a
program over a range of storage (memory and register file)
configurations. This type of retargeting is too expensive and labor
intensive to perform manually during exploration. This is
particularly true for hand-coded assembly language programs that are
optimized for specific embedded memory designs. We are developing
memory optimization transformations that synergistically optimize both
code (register and memory references) and the memory hierarchy design
parameters, guided by power and area cost models.
On-line Reconfiguration
Transition management:
We are developing techniques for rapid prototyping of code for
managing runtime reconfiguration in hybrid control systems, where mode
changes require careful handling of reconfiguration strategies. This
integrates hybrid modeling and simulation (for specifying and
validating transition strategies) with a generic transition management
pattern built on a Real-Time CORBA-based platform for reconfigurable
control systems. Code generation is performed from the hybrid models
to transition management code. This allows hybrid systems and their
reconfiguration strategies to be prototyped and validated at an early
stage in development and for the strategies to be directly transferred
into the control system software without a separate, manual
reimplementation step.
Binary Reverse Engineering
Decompilation/Disassembly:
What do executables reveal? This project is studying the state of the
art of disassembly and decompilation tools and of existing software
protection mechanisms. We are developing an experimentation framework
for evaluating binary reverse engineering tools, which we call BinREEF
(Binary Reverse Engineering Experiment Framework). This includes a
set of C++ and Java benchmark binary programs representing varying
degrees of obfuscation (e.g., stripped vs. not, optimized
vs. unoptimized) and a set of reverse engineering tasks ranging from
common, general questions (e.g., recovering the calling relationships)
to application-specific tasks (e.g., recovering key parameters from a
particular benchmark program).
Binary Reverse Engineering Publications
For more information, please contact: Linda Wills / Linda.wills@ece.gatech.edu
/ (404) 894-4565