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I3DS Group

Muhannad S. Bakir

Georgia Tech
 
 
 
 
 
 
Publications & Patents

 

Book:

  1. M. Bakir and J. Meindl (Eds.), Integrated Interconnect Technologies for 3D Nanoelectronic Systems, Artech House, 2009. (16 chapter; 550-pages)

Front & Back Covers (.pdf)

Book Outline (.pdf)

Forward (.pdf)

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Book Chapters:

  1. M. Bakir, G. Huang, and B. Dang, “3D Integration: Limits and Opportunities,” in Coupled Data Techniques, R. Ho and R. Drost (Eds.), Chapter 1, Springer, 2010. (invited)
  2. M. Bakir and J. Meindl, “Revolutionary Silicon Ancillary Technologies for the Next Era of Gigascale Integration,” in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.
  3. B. Dang, M. Bakir, D. Sekar, C. King, and J. Meindl, “Single and 3D Chip Cooling using Microchannels and Fluidic I/Os,” in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009. (invited)
  4. G. Huang, K. Shakeri, A. Naeemi, M. Bakir, and J. Meindl, “On-Chip Power Supply Noise Modeling and Chip/Package Co-Design of Gigascale and 3D Integrations,” in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009. (invited)
  5. M. Bakir, “Nanoimprint Lithography for Semiconductor and Interconnect Technologies,” in NanoTechnology: An Open Text, S. Campbell (Ed.), NSF NNIN 2007. (invited)

Granted U.S. Patents:

  1. M. Bakir, H. Reed, P. A. Kohl, C. Patel, K. Martin, and J. Meindl, ”Compliant wafer-level packaging devices and methods of fabrication,” U.S. patent number 6,690,081, assigned to Georgia Tech Research Corporation, issued Feb. 10, 2004.
  2. Mule, C. Patel, J. Meindl, T. Gaylord, E. Glytsis, K. Martin, S. Schultz, M. Bakir, H. Reed, and P. Kohl, “Guided-waver optical interconnections embedded within a microelectronic wafer-level batch package,” U.S. patent number 6,785,458, assigned to Georgia Tech Research Corporation, issued Aug. 31, 2004.
  3. Mule, J. Meindl, P. Kohl, S. Schultz, T. Gaylord, E. Glytsis, R. Villalaz, M. Bakir, and H. Reed, “Backplane, printed wiring board, and/or multi-chip module-level optical interconnect layer having embedded air-gap technologies and methods of fabrication,” U.S. patent number 6,788,867, assigned to Georgia Tech Research Corporation, issued Sept. 7, 2004.
  4. Mule, C. Patel J. Meindl, T. Gaylord, E. Glytsis, K. Martin, S. Schultz, M. Bakir, H. Reed, P. Kohl, “Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package,” U.S. patent number 6,954,576 assigned to Georgia Tech Research Corporation, issued Oct. 11, 2005.
  5. M. Bakir and J. Meindl, “Dual-mode/function optical and electrical interconnects, methods of fabrication thereof, and methods of use thereof,” U.S. patent number 7,099,525 assigned to Georgia Tech Research Corporation, issued Aug. 29, 2006.
  6. M. Bakir, J. Meindl, and C. Patel, “Devices having compliant wafer-level packages with pillars and methods of fabrication,” U.S. patent number 7,132,736 assigned to Georgia Tech Research Corporation, issued Nov. 7, 2006.
  7. M. Bakir and J. Meindl, “Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof,” U.S. patent number 7,135,777 assigned to Georgia Tech Research Corporation, issued Nov. 14, 2006.
  8. M. S. Bakir and J. D. Meindl, “Microfluidic, optical, and electrical input output interconnects, methods of fabrication thereof, and methods of use thereof,” US patent # 7,266,267, Sept. 4, 2007.
  9. M. Bakir and J. Meindl, “Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof,” U.S. patent no. 7,468,558 , issued Dec. 23rd, 2008.
  10. A. Mule, H. Thacker, M. Bakir, J. Meindl, T. Gaylord, K. Martin, and P. Kohl, “High input/output density optoelectronic probe card for wafer-level test of electrical and optical interconnect components, methods of fabrication, and methods of use,” U.S. patent no. 7,554,347, assigned to Georgia Tech Research Corporation, issued Jun. 30th, 2009.
  11. P. Kohl, A. He, T. Spencer, M. Bakir, “Integrated circuit interconnects with coaxial conductors,” U.S. patent no. 7,798,817, assigned to Georgia Tech Research Corporation, issued sept. 21st, 2010.
  12. M. Bakir, D. Sekar, B. Dang, C. King, and J. Meindl, “3-D ICs with microfluidic interconnects and methods of constructing same,” U.S. patent no. 7,928,563, assigned to Georgia Tech Research Corporation, issued Apr. 19th, 2011.
  • +10 other pending US patents and invention disclosures

Conference Tutorials:

  1. Heat Removal and Power Delivery for 3D Integration, IEEE Int. Solid State Circuits Conf (ISSCC) 2007. (invited)
  2. Chip-level and Input/Output Interconnects for Gigascale SoCs: Limits and Opportunities, IEEE System-on-Chip Conf. 2006, with A. Naeemi.

Discussion Panels:

  1. Design of 3D Chip Stacks, IEEE Int. Solid State Circuits Conf (ISSCC) 2007. (invited)
  2. Interconnect Solutions and 3D Integration for Low Power, Minimum Energy Electronics Forum, SRC/ATIC/NSF, Abu Dhabi UAE, 2010. (invited)

Refereed Journal Papers:

  1. M. S. Bakir, H. A. Reed, A. V. Mule, J. Jayachandran, P. A. Kohl, T. K. Gaylord, K. P. Martin, and J. D. Meindl, “Chip-to-module interconnections using 'Sea of Leads' technology,” MRS Bulletin, vol. 28, no. 1, pp. 61-67, Jan. 2003. (invited)
  2. D. C. Keezer, C. S. Patel, M. S. Bakir, Q. Zhou, and J. D. Meindl, “Electrical test strategies for a wafer-level packaging technology,” IEEE Trans. Electron. Packag. Manufac., vol. 26, no. 4, pp. 267-272, Oct. 2003.
  3. M. S. Bakir, T. K. Gaylord, K. P. Martin, and J. D. Meindl, “Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections,” IEEE Photon. Technol. Lett., vol. 15, no. 11, pp. 1567-1569, Nov. 2003.
  4. M. S. Bakir, H. A. Reed, H. D. Thacker, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI),” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2039-2048, Oct. 2003.
  5. M. S. Bakir, T. K. Gaylord, O. O. Ogunsola, E. G. Glytsis, and J. D. Meindl, “Optical transmission of polymer pillars for chip I/O optical interconnections,” IEEE Photon. Technol. Lett., vol. 16, no. 1, pp. 117-119, Jan. 2004.
  6. M. S. Bakir and J. D. Meindl, “Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration,” IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1069-1077, Jul. 2004.
  7. M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, “Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors,” IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1084-1090, Jul. 2004.
  8. M. S. Bakir, B. Dang, R. Emery, G. Vandentop, P. A. Kohl, and J. D. Meindl, “Sea of Leads compliant I/O interconnection process integration for the ultimate enabling of chips with low-k interlayer dielectrics,” IEEE J. Adv. Packag.,vol. 28, no. 3, pp. 488-494,2005.
  9. B. Dang, M. S. Bakir, C. S. Patel, H. D. Thacker, and J. D. Meindl, “Sea-of-Leads MEMS I/O interconnects for low-k IC packaging,” IEEE J. Microelectromechanical Systems, vol. 15, no. 3, pp. 523-530, 2005.
  10. B. Dang, M. S. Bakir, and J. D. Meindl, “Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink,” IEEE Electron Device Letters, vol. 27, no. 2, pp. 117-119, Feb 2006.
  11. Ogunsola, H. D. Thacker, B. L. Bachim, M. S. Bakir, J. Pikarsky, T. K. Gaylord, and J. D. Meindl, “Chip-level waveguide-mirror-pillar optical interconnect structure,” IEEE Photon. Technol. Lett., vol. 18, no. 15, pp. 1672- 1674, 2006.
  12. L. Glebov, D. Bhusari, P. Kohl, M. Bakir, J. Meindl, and M. G. Lee, “Flexible pillars for displacement compensation in optical chip assembly,” IEEE. Photon. Technol. Lett., vol. 18, no. 6, pp. 974-976, 2006.
  13. M. Bakir, B. Dang, O. Ogunsola, R. Sarvari, and J. Meindl, “Electrical and optical chip I/O interconnections for gigascale systems,” IEEE Trans. Electron Dev., vol. 54, no. 9, pp. 2426-2437, Sept. 2007.
  14. M. Bakir, A. Glebov, M. Lee, P. Kohl, and J. Meindl, “Mechanically flexible chip-to-substrate optical interconnections using optical pillars,” IEEE Trans. Adv. Packaging, vol. 31, no. 1, pp. 143-153, 2008.
  15. D. Sekar, C. King, B. Dang, M. Bakir, J. Meindl, “Removing heat from 3D stacked chips,” Future Fab International, Vol. 29, vol. 4, pp. 80-85, April 2009. (invited)
  16. M. Bakir, G. Huang, D. Sekar, and C. King, “3D system integration: power delivery, cooling, and signaling,” IETE Technical Review, vol. 26, no. 6, pp. 407-416, 2009. (invited) IETE-CDIL Award for Industry (Best Journal Paper Award from IETE)
  17. B. Dang, M. Bakir, D. Sekar, and J. Meindl, “Single and 3D chip cooling using microchannels and microfluidic chip input/output (I/O) interconnects,” IEEE Trans. Adv. Packaging, vol. 3, no. 1, pp. 79-87, Feb. 2010.
  18. J.-H Lai, H. S. Yang, H. Chen, C. King, J. Zaveri, R. Ravindran, and M. Bakir, "A 'mesh' seed layer for improved through-silicon-via fabrication," J. Micromech. Microeng., vol. 20., pp. 025016(+06), 2010.
  19. G. Huang, M. Bakir, A. Naeemi, and J. Meindl, “Power delivery for 3-D chip stacks: physical modeling and design implication,” IEEE Trans. Adv. Packaging, 2010. (accepted for publication)
  20. H.-S. Yang and M. Bakir, "Design, fabrication and characterization of freestanding mechanically flexible interconnects using curved sacrificial layer," IEEE Trans. on Components, Packaging and Manufacturing Technology, submitted.
  21. A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of high aspect ratio nanoscale TSVs," J. of Vacuum Science and Technology B, submitted.

Refereed Conference Proceedings:

  1. Naeemi, C. S. Patel, M. S. Bakir, P. Ha-Zarkesh, K. P. Martin, and J. D. Meindl, “Sea of Leads: a disruptive paradigm for a system on a chip,” in Proc. Int. Solid State Circuits Conf., 2001, pp. 280-281.
  2. H. A. Reed, M. S. Bakir, C. S. Patel, K. P. Martin, J. D. Meindl, and P. A. Kohl, “Compliant wafer level package with embedded air-gaps for Sea of Leads I/O interconnections,” in Proc. Int. Interconnect Technol. conf., 2001, pp. 151-153. (invited)
  3. J. D. Meindl, R. Venkatesan, J. A. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. S. Bakir, T. Mule, P. A. Kohl, and K. P. Martin, “Interconnecting device opportunities for gigascale integration (GSI),” in Proc. Int. Electron Devices Meeting, 2001, pp. 525-528.
  4. M. S. Bakir, H. A. Reed, A. V. Mule, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Sea of Leads characterization and design for compatibility with board level optical waveguide interconnection,” in Proc. Custom Integrated Circuits Conf., 2002, pp. 491-494.
  5. Best Conference Paper Award: M. S. Bakir, H. A. Reed, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Sea of Leads ultra-high density compliant wafer level packaging technology,” in Proc. Electronic Components and Technol. Conf., 2002, pp. 1087-1094. ; Paper featured in multiple trade journal articles.
  6. H. D. Thacker, M. S. Bakir, D. Keezer, K. P. Martin, and J. D. Meindl, “Compliant probe substrates for testing high pin-count chip scale packages,” in Proc. Electronic Components and Technol. Conf., 2002, pp. 1188-1193.
  7. M. S. Bakir, H. D. Thacker, Z. Zhou, K. P. Martin, and J. D. Meindl, “Sea of leads microwave characterization and process integration with FEOL & BEOL,” in Proc. Int. Interconnect Technol. Conf., 2002, pp. 116-118.
  8. A. V. Mule, M. S. Bakir, J. Jayachandran, R. Villalaz, H. Reed, N. Agrawal, S. Ponoth, J. Plawsky, P. Persans, P. Kohl, K. Martin, E. Glytsis, T. Gaylord, and J. Meindl, “Optical waveguides with embedded air-gap cladding integrated within a Sea-of-Leads (SoL) wafer-level package,” in Proc. Int. Interconnect Technol. Conf., 2002, pp. 122-124. Paper featured in multiple trade journal articles.
  9. M. S. Bakir, A. Mule, T. Gaylord, P. Kohl, K. Martin, and J. Meindl, “Sea of dual-mode polymer pillar I/O interconnections for gigascale integration,” in Proc. Int. Solid-State Circuits Conf., 2003, pp. 372-373. (Figures from paper were used to publicize conference) Paper featured in multiple trade journal articles.
  10. M. S. Bakir, R. A. Villalaz, O. O. Ogunsola, T. K. Gaylord, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Sea of polymer pillars: dual-mode electrical-optical input/output interconnections,” in Proc. Int. Interconnect Technol. Conf., 2003, pp. 77-79.
  11. M. S. Bakir, B. Dang, R. Emery, G. Vandentop, K. P. Martin, P. A. Kohl, and J. D. Meindl, “Chip integration of Sea of Leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics,” in Proc. Electronic Components and Technol. Conf., 2004, pp. 1167-1173.
  12. M. S. Bakir and J. D. Meindl, “Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration,” in Proc. Electronic Components and Technol. Conf., 2004, pp. 1-6.
  13. B. Dang, C. Patel, H. D. Thacker, M. S. Bakir, K. P. Martin, and J. D. Meindl, “Optimal implementation of Sea-of-Leads (SoL) compliant interconnect technology,” in Proc. IEEE Int. Interconnect Technol. Conf., 2004, pp. 99-101.
  14. K. Shakeri, M. S. Bakir, and J. D. Meindl, “Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution,” in Proc. IEEE Int. System-on-Chip Conf., 2004, pp. 78-81.
  15. B. Dang, M. S. Bakir, K. P. Martin, and J. D. Meindl, “Assembly and reliability assessment of Sea-of-Leads compliant wafer level package,” in Proc. IMAPS Int. Symp. on Microelectronics, 2004, pp. 7-14.
  16. M. S. Bakir and J. D. Meindl, “Wafer-level packaging of optoelectronic devices using Sea of Leads electrical and optical I/O interconnections,” in Proc. IEEE LEOS Annual Meeting, 2004, pp. 583-584. (invited)
  17. B. Dang, P. J. Joseph, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, “A chip-scale cooling scheme with on-chip heat sink and integrated microfluidic I/O interconnects,” in Proc. SRC TECHCON, 2005.
  18. O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, J. Meindl, “Mirror-enabled polymer pillar optical I/O interconnects for gigascale integration,” in Proc. SRC TECHCON, 2005. 
  19. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, “Probe module for wafer-level testing of gigascale chips with polymer pillar-based electrical and optical I/O interconnects,” in Proc. SRC TECHCON, 2005.
  20. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, “High-density probe substrate for testing optical interconnects,” in Proc. IEEE Int. Interconnect Technol. Conf., 2005, pp.159-161.
  21. H. Thacker, O. Ogunsola, M. Bakir, J. Meindl, “Probe Module for Wafer-level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects,” in Proc. ASME InterPACK, 2005.
  22. B. Dang, P. J. Joseph, X. Wei, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, “A chip-scale cooling scheme with on-chip heat sink and integrated microfluidic I/O interconnects,” in Proc. ASME InterPACK, 2005, paper num. 73416.
  23. B. Dang, P. Joseph, M. Bakir, P. Kohl, J. Meindl, “Fabrication, assembly and testing of an on-chip microfluidic heat sink,” in Proc. Int. Symp. of Microelectronics, 2005, TP2:pp.1-5.
  24. Best Student Conference Paper Award: B. Dang, P. Joseph, M. Bakir, T. Spencer, P.A. Kohl, J.D. Meindl, “Wafer level microfluidic cooling interconnects for GSI,” in Proc. IEEE Int. Interconnect Technol. Conf., 2005, pp.180-182.(Figures from paper were used to publicize conference) Paper featured in multiple trade journal articles.
  25. M. Bakir, B. Dang, H. Thacker, O. Ogunsola, R. Ogra, and J. Meindl, “Dual-mode electrical-optical flip-chip I/O interconnects and a compatible probe substrate for wafer-level testing,” in Proc. Electronic Components and Technol. Conf., 2006, pp. 768-775.
  26. H. Ate, M. Bakir, S. Allen, P. Kohl, “Fabrication of compliant, copper-based chip-to-substrate connections,” in Proc. Electronic Components and Techn. Conf., 2006, pp. 29- 34.
  27. Best Student Conference Paper Award: O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, J. Meindl, “Polymer pillars as optical I/O for gigascale chips using mirror-terminated waveguides,” IEEE Int. Interconnect Technol. Conf.,2006, pp. 170- 172.(Figures from paper were used to publicize conference) Paper featured in multiple trade journal articles.
  28. K.-N. Chen, M. Bakir, J. Meindl, and R. Reif, “Copper interconnect bonding for polymer pillar I/O interconnects and three-dimensional (3D) integration applications,” in Proc. TMS Electronics Materials Conf., 2006.
  29. H. Thacker, O. Ogunsola, A. Carson, M. Bakir, and J. Meindl, “Optical through-wafer interconnects for 3D hyper-integration,” in Proc. IEEE LEOS, 2006, pp. 28-29.
  30. M. S. Bakir, P. A. Kohl, A. L. Glebov, E. Elce, D. Bhusari, M. G. Lee, and J. D. Meindl, “Flexible polymer pillars for optical chip assembly: materials, structures, and characterization,” in Proc. SPIE Photonics West, 2007. (invited)
  31. M. Bakir and J. Meindl, “Fully compatible low cost electrical, optical, and fluidic I/O interconnect networks for ultimate performance 3D gigascale systems,” in Proc. Int. 3D System-in-Chip Conf., 2007. (invited, Tokyo,  Japan)
  32. Outstanding Conference Paper Award: M. Bakir, B. Dang, O. Ogunsola, and J. Meindl, “Trimodal’ wafer-level package: fully compatible electrical, optical, and fluidic chip I/O interconnects,” in Proc. in Proc. Electronic Components and Technol. Conf., 2007.
  33. M. Bakir, B. Dang, and J. Meindl, “Electrical, optical, and thermofluidic chip I/O interconnections,” in Proc. ASME InterPACK, 2007.
  34. Best Invited Conference Paper Award: M. Bakir, B. Dang, and J. Meindl, “Revolutionary nanosilicon ancillary technologies for ultimate-performance gigascale systems,” in Proc. IEEE Custom Integrated Circuits Conf., 2007. (invited) (Figures from paper were posted on the conference website)
  35. M. Bakir, B. Dang, G. Huang, and J. Meindl, “Limits and opportunities for heat removal and power delivery to gigascale systems,” in Proc. SEMATECH Thermal and Design Issues in 3D ICs, 2007. (invited) Paper featured in multiple trade journal articles.
  36. G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. Meindl, “Power delivery for 3D chip stacks: physical modeling and design implication,” in Proc. IEEE 16th Conf. Electrical Performance and Electronic Packaging, 2007, pp. 205-208.
  37. C.R. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, J. Meindl, “Assembly techniques for microfluidic networks in three-dimensional integrated circuits,” SRC TECHCON, 2007.
  38. Motorola Electronic Packaging Fellowship Student Paper Award ($21,000 stipend): C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, and J. Meindl, “3D stacking of chips with electrical and microfluidic I/O interconnects,” in Proc. Electronic Components and Technol. Conf., 2008, pp. 1-7.
  39. Best Student Conference Paper Award: D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir, and J. Meindl, “A 3D-IC technology with integrated microchannel cooling,” in Proc. IEEE Int. Interconnect Technol. Conf., 2008, pp. 13-15. (Figures from paper were used to publicize conference) Paper featured in multiple trade journal articles.
  40. C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, and J. Meindl, “3D stacking of chips with electrical and microfluidic I/O interconnects,” in Proc. SRC TECHCON, 2008.
  41. M. S. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, G. Huang, A. Naeemi, and J. D. Meindl, “3D heterogeneous integrated systems: liquid cooling, power delivery, and implementation,” in Proc. IEEE Custom Integrated Circuits Conf., 2008, pp.663-670. (invited)
  42. M. S. Bakir, C. King, D. Sekar, and B. Dang, “Electrical, optical, and fluidic interconnect networks for 3D heterogeneous integrated systems,” in Proc. IEEE Avionics, Fiber-Optics and Photonics Conf., 2008, pp.7-8. (invited)
  43. M. Bakir and G. Huang, “Power delivery, signaling and cooling in 3D integrated systems,” in Proc. MRS Spring Meeting, 2009. (invited)
  44. Best in Session Paper Award:C. King J. Zaveri, H. Yang, M. Bakir, and J. Meindl “Electro-fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs,” in Proc. SRC TECHCON, 2009.
  45. J. Zaveri, C. King, H. Yang, and M. Bakir, “Wafer level batch fabrication of Silicon microchannel heat sinks and electrical through silicon vias” in Proc. SRC TECHCON, 2009.
  46. Best Student Paper Award and Best Paper in Session Award:J. Zaveri, C. King Jr., H.S. Yang, M.S. Bakir, “Wafer level batch fabrication of silicon microchannel heat sinks and electrical through silicon vias for 3D ICs,” IMAPS 42nd International Symposium on Microelectronics, 2009.
  47. H. S. Yang and M. Bakir, "Interconnect technologies for 3D integration of CMOS and MEMS," in Proc. MRS Spring Meeting, 2010. (invited)
  48. C. King, J. Zaveri, M. Bakir, and J. Meindl, "Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. IEEE Electronic Components and Technology Conference, pp. 822-828, 2010.
  49. H. S. Yang and M. Bakir, "Mechanically Flexible Interconnects with High Out-of-Plane Range-of- Movement and Thick Wafer Through Silicon Vias for CMOS and MEMS Integration," in Proc. IEEE Electronic Components and Technol. Conf., pp. 822-828, 2010.
  50. R. Ravindran, J. A. Sadie, K. E. Scarberry, H. S. Yang, M. S. Bakir, J. F. McDonald, and J. D. Meindl, “Biochemical Sensing with an Arrayed Silicon Nanowire Platform," in Proc. IEEE Electronic Components and Technol. Conf., pp. 1015-1020, 2010.
  51. H. S. Yang, R. Ravindran, M.S. Bakir and J.D. Meindl, "A 3D Interconnect System for Large Biosensor Array
    and CMOS Signal-Processing IC Integration,” in Proc. of IEEE Int. Interconnect Technol. Conf., 2010.
  52. Best in Session Paper Award:H. S. Yang and M. Bakir, "3D integration of CMOS and MEMS using MFI and TSV," in Techcon, 2010.
  53. M. Bakir, P. Thadesar, C. King, J. Zaveri, H. Yang, C. Zhang, Y. Zhang, “Revolutionary innovation in system interconnection: A new era for the IC,” in Proc. Photonics West, 2011, in-press. (invited)
  54. Y. Zhang, C. King, J. Zaveri, and M. Bakir, “Coupled electrical and thermal 3D IC centric microliquid cooling heat sink design and technology,” in Proc. IEEE Electronic Components and Technology Conference, 2011, in-press.
  55. M. Parekh, P. Thadesar and M. Bakir, “Electrical, optical, and fluidic through-silicon vias for silicon interposer applications,” in Proc. IEEE Electronic Components and Technology Conference, 2011, in-press.

Refereed Workshop Proceedings:

  1. M. S. Bakir, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Sea of Leads (SoL) packaging technology,” in Proc. Int. Workshop on Wafer Level CSP & Flip Chip Packaging, 2002, pp. 8.
  2. H. A. Reed, M. S. Bakir, K. P. Martin, S. Bidstrup-Allen, and P. A. Kohl, “Embedded air-cavities for compliant wafer-level packaging,” in Proc. Int. Workshop on Wafer Level CSP & Flip Chip Packaging, 2002, pp. 21.

Journal Papers (not reviewed):

  1. M. S. Bakir, A. V. Mule, H. D. Thacker, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Next-generation Sea-of-Leads (SoL) compliant wafer-level package technologies,” Semiconductor International Magazine, vol. 25, no. 4, pp. 61-64, Apr. 2002.

Presentations (without proceedings):

  1. M. Bakir, “NIL, EBL, and Trimodal I/Os,” NNIN Forum on Soft Lithography, Harvard University, Cambridge, MA, Nov. 1, 2006.
  2. M. Bakir and J. Meindl, “Compatible electrical, optical, and fluidic I/O and through-wafer interconnects for 3D integration,” IBM Workshop on 3D Integration, IBM T. J. Watson Research Center, Yorktown, NY, Mar. 7, 2006. (invited)
  3. M. Bakir, “Overview of nanoimprint lithography,” Nanoimprint Education at the Microelectronics Research Center, Georgia Tech, Atlanta, 2006-2008.
  4. M. Bakir, “Introduction to Nanoimprint and soft lithography,” Nano@Tech Meeting, Georgia Tech, Atlanta, GA, Jan. 29, 2007. (invited)
  5. M. Bakir, “Electrical, optical, and fluidic I/O & through-wafer interconnects for 3D systems,” IFC Web Seminar, April 17, 2007.
  6. M. Bakir and J. Meindl, “Revolutionary nanosilicon ancillary technologies for ultimate-performance gigascale systems,” Nanobiofluidic MEMS Workshop, Georgia Tech, Atlanta, GA, Nov. 29, 2007. (invited)
  7. M. Bakir, “New paradigm to 3D system integration and testing: electrical, optical, and fluidic interconnects” Web Seminar, Intel Corporation, July 23rd, 2008. (invited)
  8. M. Bakir, "Revolutionary Silicon Ancillary Technologies for the Next Era of Gigascale Systems," Sun Labs, CA, April 2009. (invited)
  9. M. Bakir, "Interconnect Solutions and 3D Integration for Low Power," Minimum Energy Electronics Forum, ATIC/SRC, Abu Dhabi UAE, May 2010. (invited)
  10. M. Bakir, "3D Heterogeneous Technologies for [Memory-Processor]  & [CMOS-MEMS/Sensor] Stacking," IBM T. J. Watson Research Center, Yorktown, NY, April, 2010. (invited)
  11. M. Bakir, "3D Stacking: A New Era for the Integrated Circuit," SUNY-Albany, NY, April, 2010. (invited)
  12. + others