My research interests include:

Three-dimensional (3D) system integration, chip I/O interconnect networks (electrical, optical, and fluidic), chemical and biosensors and their integration with CMOS circuitry, advanced cooling and power delivery for 3D systems, nanofabrication technology.

Research Grants ($1.2 M total):

Title: “IBSI Collaborative Graduate Student Fellowship Program: Biosensors”

PIs: J. Meindl, M. Bakir, and J. McDonald
Funding Organization: Integrative BioSystems Institute, Georgia Tech
Duration: July 2008-June 2009
 

Title: “Development of a Nanosensor for the Detection of Cancer Biomarkers”

PIs: J. Meindl, M. Bakir, and J. McDonald
Funding Organization: Integrative BioSystems Institute, Georgia Tech
Duration: July 2008-June 2009

Title: “Interconnect and Wafer-Level Packaging Technologies for CMOS-MEMS Integration”

PIs: M. Bakir & J. Meindl
Funding Organization: Semiconductor Research Corporation (SRC)
Duration: July 2008-June 2011

Title: “Interconnect Networks for Three-Dimensional Gigascale System-on-a Chip”

PIs: M. Bakir & J. Meindl
Funding Organization: National Science Foundation (NSF)
Duration: May 2007-April 2010

Title: “Electrical, Optical, and Fluidic Chip I/O Interconnects”

PIs: M. Bakir & J. Meindl
Funding Organization: Interconnect Focus Center (IFC)
Duration: Sept. 2006-Aug. 2009

Title: “Compliant, Copper-based Chip-to-Substrate Connections”

PIs: P. Kohl & M. Bakir
Funding Organization: Semiconductor Research Corporation (SRC)
Duration: July 2005-June 2008

Research Abstract:

As gigascale silicon technology approaches the 50 nm generation and beyond, the performance of a monolithic system-on-a-chip (SoC) has failed by progressively greater margins to reach the “intrinsic limits” of each particular generation of technology. The root cause of this failure is the fact that the capabilities of monolithic silicon technology per se have vastly surpassed those of the ancillary or supporting technologies that are essential to the full exploitation of a high performance SoC. The most serious obstacle that blocks fulfillment of the ultimate performance of a SoC is inferior heat removal. The increase in clock frequency of a SoC has been virtually brought to a halt by the lack of an acceptable means for removing, for example, 200 W from a 15x15 mm die thereby motivating architectural migration to multi-core microprocessors. In addition, the inability to remove >100 W/cm2 per stratum is the key limiter to 3D integration of a microprocessor stack.  A huge deficit in chip input/output (I/O) bandwidth due to insufficient I/O interconnect density is the second most serious deficiency stalling high performance gains. The excessive access time of a chip multiprocessor (CMP) for communication with its off-chip main memory is a direct consequence of the lack of, for example, a low latency 100 THz aggregate bandwidth I/O signal network. The pace of advances in latency and bandwidth of I/O signal interconnect networks has been relatively stagnant compared to on-chip signal interconnect networks. Lastly, SoC performance has been severely constrained by inadequate I/O interconnect technology capable of supplying, for example, 200-400 A at 0.7 V to a CMP with ever decreasing noise margins.
A critical technical hurdle to the above grand challenges is the realization of a low cost chip-scale integrated I/O interconnect network that is capable of addressing the heat removal, I/O bandwidth, and power delivery requirements for 3D SoC. Thus, the goal of our research is to experimentally demonstrate and derive physical models for fully compatible low cost electrical, optical and fluidic (trimodal) I/O and trimodal through-wafer interconnect (TWI) technologies that will enable the most compact 3D SoC. In other words, the critical feature of our proposed research is to develop, integrate, and model all significant I/O interconnect technologies that are critical to the realization of 3D SoC. The overarching strategy of our novel approach is to “extend low-cost wafer-level batch processing,” the key to the success of Si technology, to the ancillary technologies that have now become the “millstone around the neck of Si technology itself.”

Images of Electrical, Optical, and Fluidic Chip I/O Interconnects