I3DS Group
Muhannad S. Bakir
Georgia Tech
| |
| Home |
| Research |
| Publications & Patents |
| People |
| Awards |
| Press Coverage |
| Collaboration |
| Research |
My research interests include: Three-dimensional (3D) system integration, chip interconnect networks (electrical, optical, and fluidic), chemical and biosensors and their integration with CMOS circuitry, advanced cooling and power delivery for 3D systems, carbon-based interconnections, and nanofabrication technology.
Research Grants (>$3 M total): Title: “Coupled Electrical and Thermal Design and Technology for 3D ICs”
Title: “Trimodal Chip I/O and Substrate Interconnects for Single and 3D Chips”
Title: “Energy Efficient Advanced 3D Computing Racks Enabled Through Microfluidic Heat Removal”
Title: “IBSI Collaborative Graduate Student Fellowship Program: Biosensors”
Title: “Development of a Nanosensor for the Detection of Cancer Biomarkers”
Title: “Interconnect and Wafer-Level Packaging Technologies for CMOS-MEMS Integration”
Title: “Interconnect Networks for Three-Dimensional Gigascale System-on-a Chip”
Title: “Electrical, Optical, and Fluidic Chip I/O Interconnects”
Title: “Compliant, Copper-based Chip-to-Substrate Connections”
Summary: As gigascale silicon technology approaches the 45 nm generation and beyond, the performance of a monolithic system-on-a-chip (SoC) has failed by progressively greater margins to reach the “intrinsic limits” of each particular generation of technology. The root cause of this failure is the fact that the capabilities of monolithic silicon technology per se have vastly surpassed those of the ancillary or supporting technologies that are essential to the full exploitation of a high performance SoC. The most serious obstacle that blocks fulfillment of the ultimate performance of a SoC is inferior heat removal. The increase in clock frequency of a SoC has been virtually brought to a halt by the lack of an acceptable means for removing, for example, 200 W from a 15x15 mm die thereby motivating architectural migration to multi-core microprocessors. In addition, the inability to remove >100 W/cm2 per stratum is the key limiter to 3D integration of a microprocessor stack. A huge deficit in chip input/output (I/O) bandwidth due to insufficient I/O interconnect density is the second most serious deficiency stalling high performance gains. The excessive access time of a chip multiprocessor (CMP) for communication with its off-chip main memory is a direct consequence of the lack of, for example, a low latency 100 THz aggregate bandwidth I/O signal network. The pace of advances in bandwidth of I/O signal interconnect networks has been relatively stagnant compared to on-chip signal interconnect networks. Lastly, SoC performance has been severely constrained by inadequate I/O interconnect technology capable of supplying, for example, 200-400 A at 0.7 V to a CMP with ever decreasing noise margins. Our research aims to model the above issues and identify and implement the most promising technologies to address these challenges.
|