My previous research has been on placement for configurable architectures, thermal-performance tradeoffs in 2D and 3D microarchitectural floorplanning, power-supply-noise-aware microarchitectural floorplanning, and multi-granularity multi-objective floorplanning for multi-core architectures.

My current research is on the effects of through silicon vias (TSVs) on the power supply network in many-tier systems. My work assumes that the mechanical problems with 3D integration have been solved and stacking is limited more by electrical and thermal problems. I have studied novel TSV distributions, performed scaling studies and developed a wire-pitch scaling algorithm for optimizing the power network of many-tier systems.

My future work will focus on optimizing the density and placement of "additional" TSVs, where additional means TSVs that are not vertically aligned with the C4 bumps.