Introduction to MOSFET Modeling

The goals of this second lab project are

• to become familier with static MOSFETs: experimental data and models, both above-threshold and subthreshold behavior
• to understand how accurately SPICE models MOSFETs

You will take static measurements of MOSFET channel current versus gate voltage and source voltage for both an nFET and a pFET.

For the experimental measurments of drain-to-source current as a function of gate voltage, you should:

• Fit the theoretical expression in two regions of operation.

  First, perform a curve fit focused on the above-threshold region (a polynomial curve fit). From the above-threshold region, you should extract the threshold voltage (V_T) as a function of K and kappa . (Yes, do not assume kappa = 1) From your measured data, identify the channel current level when the device is biased with a gate voltage equal to threshold voltage (i.e. the threshold current, I_th).

  Second, perform a curve fit focused on the subthreshold region (an exponential curve fit). From the subthreshold graph, you should extract a value for kappa and I₀ .

• Then using the above threshold parameters, (that is you will not need kappa or I₀ for this modeling) perform a SPICE simulation (Must be EKV model) corresponding to this measurement of drain current versus gate voltage.

• You should include two figures for this experiment showing I_ds versus V_g curves: one plot showing above-threshold operation (linear or square-root current), and one plot showing subthreshold operation (exponential current). In each of these two plots, you should show the experimental data, the appropriate curve fit, and your SPICE simulation results merged together on a single plot. (The simulation results must be EKV model). Indicate where the simulation agrees and does not agree with measured results.

• Compute g_m / I for all values of current, and make a third figure of g_m / I (linear scale) versus I (log scale).

For the experimental measurements of the source current as a function of source voltage from an nFET and pFET for fixed voltages on the gate, drain, and bulk, you should:

• Fit the theoretical expression in two regions of operation.

  First, perform a curve fit focused on the above-threshold region (a polynomial curve fit). From the above-threshold region, you should extract the threshold voltage (V_T) as a function of K and kappa that is different from the gate sweep measurement .

  Second, perform a curve fit focused on the subthreshold region (an exponential curve fit). From the subthreshold graph, you should extract a value for U_T. Does this value agree with the expected value at room temperature? The data was taken at a temperature nearly equal to 300K.

• Then using the above threshold parameters, (that is you will not need kappa or I₀ for this modeling) perform a SPICE simulation corresponding to this measurement of drain current versus source voltage.

• You should include two figures for this experiment showing I_ds versus V_s curves: one plot showing above-threshold operation (linear or square-root current), and one plot showing subthreshold operation (exponential current). In both plots you should show the experimental data, the appropriate curve fit, and your SPICE simulation results. Indicate where the simulation agrees and does not agree with measured results.

Finally, as a result of these two data sets, you should be able to solve for K and kappa.

For the experimental measurements of the source current as a function of drain voltage from an nFET and pFET for fixed voltages on the gate, drain, and bulk, you should: ( the source voltage is connected to ground or 0V, and the gate was connected to 0.5V for the nFET down from Vdd of 2.4V for the nFET)

Find the Early voltage from measured data of source current versus drain voltage. Perform the appropriate curve fit through the saturated range of the data. It is helpful to select a one to two volt range of drain voltage for these fits

Perform a SPICE simulation that gives similar results using the parameters you previously obtained.

Make a plot of the data, indicate the saturated and ohmic regions, and resulting curve fit to these two regions. Identify the drain-to-source voltage was required to reach saturation. Identify on your graphs where the devices are in saturation and where they are in the ohmic regime. Label these curves with the values of I_dsat, and and V_A. Is this curve taken in subthreshold or above-threshold operation? How could you tell just from your data plot?

Experimental data:

• Static measurements of channel current (nFET) versus gate voltage. The source was held to 0V, and the drain was held to 2.4V so that the device would stay in the saturation regime. The data is in two column format. Data: [gate voltage, channel current]
• Static measurements of channel current versus source voltage. We are measuring the source current as a function of source voltage from an nFET for fixed voltages on the gate (=2.4V), drain (=2.4V), and bulk (=0V). The transistor was biased to stay in saturation throughout this sweep. The data is in two column format. Data: [source voltage, channel current]
• Static measurements of channel current versus drain voltage. We are measuring the source current as a function of drain voltage from an nFET for fixed voltages on the gate (=0.4V), source (=0V), and bulk (=0V). The data is in two column format. Data: [drain voltage, channel current]
• Corresponding pFET data measurements. pFET Gate Sweep , pFET Source Sweep , and pFET Drain Sweep ,

Solutions to this problem for an earlier data set:

These measurements were taken from the same nFET MOSFET fabricated in a 2.0um process.
Data1: or [gate-voltage channel-current]
Data2: or [source-voltage drain-current] : source voltage from an nFET for fixed voltages on the gate (=2V), drain (=5V), and bulk (=0V).

More Data sets
Data1: [gate-voltage channel-current]
Data2: [source-voltage drain-current] source voltage from an nFET for fixed voltages on the gate (=2V), drain (=5V), and bulk (=0V). More data for pFET device: pFET Gate Sweep and pFET Gate Sweep . W/L of this element is 6u/3u.

Magic Information

Magic has its roots as the first used tool developed at Berkeley in the 70's and 80's. Many of the students who wrote this tool went on to work on CADENCE tools, so there are some similarities. Magic is free under the GNU licences.

One good website link to the most up-to-date version: Tim's Magic-7 Webpage.

Magic is a UNIX based program (it came from Berkeley in the 80's, as did many UNIX tools), so if you are running on a version of UNIX, like linux, the installation is very straight-forward, and bug free.

One can use Magic on a PC, which couples Magic with an X-emulator, such as Xwin or Cygwin. Look at Tim's Webpage above and follow the instructions to get Cygwin. (You may also get Magic to work with Xwin or some other X11 program.) One comment on Cygwin: if you are going to emulate a three button mouse (and Magic uses a 3 button mouse), make sure these options are correctly set.... Cygwin can take a very long time to download; you may find this site a quicker way to get it. You might want to have a fast network connection available when working with this option, or it will take some time. (you can also download the files and put on your machine for installation). After you have Cygwin running, download and install Magic as directed. Make sure that the X server is actively running in the background when you start running magic. There is a way to run magic by executing a batch file, or you can just type magic -w at the Cygwin prompt (or magic -w filename to run magic and load up a layout file.) You'll need the correct technology file. For my setup, I had to put it in the folder cygwin/usr/local/lib/magic/sys/ (with other .tech files in the same directory such as scmos.tech). This same folder has an important initialization file: ".magic". You can edit the keystroke macros to your desire within this file. (Changes take effect upon starting/restarting magic.) It also will help to have a line at the bottom of this file as follows:
tech load SCN3ME_SUBM.30.tech27 -noprompt

It will help to look through several of the tutorials on Tim's webpage - I suggest you at least go through the first two and the wiring section in three. To extract, in magic type "extract" and it will extract the file for you into a separate netlist. To get a SPICE file, on the command line, type "exttospice filename". To generate a readable description of your layout (as it is submitted for fabrication), use the "cif" function (see "cif help"). Each "box" represents a polygon; you can use the "cif see" option to see how they correspond to your actual layout. (For example, "CWN" is an n-well and "CWP" is a p-well, which will be ignored by the fab for an n-well [only] process.) To generate a .gds file (a binary-stream representation of the information in the CIF file, which I will need for your final projects to route them to pads and fabricate them), use the "calma" function (see "calma help"). (In Cadence, I believe you want to do File|Export|Streamout from the CIW window in order to write out a .gds file.)

For your report submission, include your ".mag" design file for each layout you completed. Also, please stream out each file into a ".gds" file. (If you are using Cadence, then just the .gds file will suffice.)

Introduction to IC Layout Problem

Remember all simulation of MOSFET's should still be performed using an EKV model. Layout an n-channel MOSFET in a standard slice configuration and an nFET in a ring configuration: in both cases, use a W/L ratio of about 100. The "standard slice" is a rectangular active area with a straight polysillicon rectangle crossing over it to form the channel. For a ring, or "donut" transistor, you will have to estimate the width at about halfway along the channel's length around the circle. Note the process you are working in puts nFET's directly in the p-substrate, while pFET's are placed in an n-well. (Depending upon the transistor, you may or may not have to draw your n wells explicitely.) As always, ensure your final design agrees with the Design Rule Checker (DRC) - you can use the ? macro ("drc why" is the long command) to explain any DRC errors you see. Extract the resulting parameters, and compare to your theoretical expectations. (Alter the netlist if necessary to get the proper results.)