Project 4: Moving towards Amplifier Design

Remember all simulation of MOSFET's should still be performed using an EKV model.

Layout an n-channel MOSFET in a standard slice configuration and an nFET in a ring configuration: in both cases, use a W/L ratio of about 100. The "standard slice" is a rectangular active area with a straight polysillicon rectangle crossing over it to form the channel. For a ring, or "donut" transistor, you will have to estimate the width at about halfway along the channel's length around the circle. (Note the process you are working in puts nFET's directly in the p-substrate, while pFET's are placed in an n-well. Draw your n wells explicitely.) As always, ensure your final design agrees with the Design Rule Checker (DRC) - you can use the ? macro ("drc why" is the long command) to explain any DRC errors you see. Extract the resulting parameters, and compare to your theoretical expectations. (Alter the netlist if necessary to get the proper results.) Build a high-gain amplifier using both device types, using a pFET current source for both (choose the appropriate architecture for both cases). (You will need two new layouts, using the pFET current source in addition to the nFETs you've already layed out. Although the precise design of the pFET isn't important, I suggest you make the pFET current source as small as possible.) Perform a frequency response in the high-gain region for both cases, and give a single plot of the frequency response for both cases. Compare your results. Use a bias current of 1 &muA. Use no extra load capacitance, but ensure that the "parasitic" capacitances are properly accounted for in the simulation.
Layout a lateral pnp BJT device with the minimum possible emitter area: design it in such a manner as to achieve the maximum possible Beta. See the results you get from extraction from the CAD tools and discuss these in your report. (You don't need to do any simulation on the BJT.)
(You don't need to do any layout for this section - this is simulation only.) Starting with a standard Bootstrap current reference, design and simulate a current source that outputs 5&muA such that all devices remain in subthreshold operation with a Vdd operating at 3.3V. Use your existing EKV model to simulate the current references. (For the simulations of your layout above, you may use this file or your own EKV model.) Use nFETs and pFETs with a channel length of 1.8 &mum. You may use a resistor, and whatever channel widths are necessary, so long as they are no less than 1.5 &mum and no greater than 150 &mum. (If necessary, you may use multiple transistors in parallel using the multiplier option in spice.) After you have verified the proper DC operating point (of 5 &muA output current), perform a DC sweep of the power supply over a limited range (take V_dd no lower than 3V) and calculate the resulting output current sensitivity to the power supply. Finally, modify your current source to have cascode current mirrors, and again compute the output current sensitivity to the power supply. Do you have any transistors not operating in saturation? Did you need a startup circuit to get the correct simulation results? Why or why not? Discuss any methods used to get the circuit into a working operating range. Include a plot of the output current (for both cases) versus power supply.


Circuit 1		Circuit 2

Create layout designs for both circuits above that pass the design rule check (DRC) verification tool. For circuit 1, make your pFETs have a W/L = 16 um /.8 um and your nFETs be W/L = 8 um /.8 um. For circuit 2, use the same FET dimensions except for the cascode transistors. You may choose the size of these transistors, but you should justify your choice. Note that the source follower is being used as load only.
Simulate the resulting circuits after layout. For the following simulations, bias your circuits with 10 nA of current (hint: an ideal current source and a diode connected FET will make biasing simple). Maximize the output headroom of circuit 2 when choosing your cascode biases. EKV model parameters have been provided for your AC simulations.
Include a picture of your layout in your report. Since your reports are submitted electronically, it is acceptable to submit color images to differentiate between the layers.
Create a table of FET parameters (source/drain area, etc) used in your schematic.
Perform a transient simulation to generate step response plots for both circuits. Generate both step up and step down plots as well as small and large signal steps. Does the capacitance extracted from these responses fit what you would calculate based upon your layout?
Perform an AC simulation of both circuits to produce a frequency response plot. Where is the -3 dB point?

Relevant EKV Parameters

	nFET	pFET
TOX	7.8e-9	7.8e-9
CGD0	3.39e-10	2.73e-10
CGS0	3.39e-10	2.73e-10
CJ	8.935e-4	1.418e-3
PB	.8	1.0
MJ	.35	.56
CJSW	2.495e-10	2.805e-10
PBSW	1.0	1.0
MJSW	.17	.40