Project 7: A CMOS amplifier design

Specifications for the Amplifier Design

Same specifications for all designs, which are differential input, differential output amplifiers

Power supplies: 0V and 2.4V.
Gain > 100,000
Q <= 1, which is equivalent to at least 45 degrees of phase margin
CMRR > 10000
Input swing: 0V to 1.9V
Output swing: 0.4V to 2.6V
Differential input, single-ended output
Your amplifier sees a 100fF load; you may add additional load capacitance (which might be required for stability), which must be included in your layout, if desired.

Specifications that will change for each design (and will be sent to the class by e-mail...everyone will have different specifications for these parameters)

Amplifier Bandwidth
Slew Rate
Noise performance
Power dissipation

Part of the grade will be on the creativity of the design as well as meeting the specifications

In your presentation materials (some of which you will present) you need to include:

A clearly drawn figure of the circuit diagram that you have chosen. Remember that you will need to provide all additional biasing besides the two outputs of the bootstrap bias generator. Do not just give me a screen dump from CADENCE or SPICE...a cleanly drawn figure is required.
Write the fundamental equations describing your circuit's operation and how the device parameters relate to the above specifications.
Write a MATLAB script to solve for the resulting specification outputs given your input parameters. Numerically (by having MATLAB compute ranges of values) find a solution that satisfies your specifications. Clearly, some intuition will be helpful here. Alternatatively, if you can input all of your parameters and solve for your solution is acceptable, or some combination of the two techniques is acceptable. Send your MATLAB .m file as an attachment.
Layout your circuit design. Your circuit must fit into a horizontal pitch of 50um (0.35um TSMC process). Layout will not be accepted if it does not fit the pitch. On both sides of your design, we have substrate tie-downs, which will be located 1.5um away from the 50um edge. This approach will help isolate your design from other student's designs. Your layout must be on lambda or 1/2 lambda grid spacing.
You have two outputs (the nFET current source and pFET current source) from a bootstrap current source, that uses cascoded current mirrors. You must provide any additional biasing circuitry, which also must simulate for your design. You might want to include a bootstrap current source in your simulations. At the top of your cell, you will have your positive (4.2um from left edge) and your negative (4.2um from right edge) inputs. At the bottom of your cell will be your outputs (in center of your cell no explicit placement), and your nFET bias (8.4um from left edge) / pFET bias (8.4um from right edge). Power will be at 13um from left edge and right edge, and gnd will be at the edges of the cell (which also connects to the tie downs). The output will be buffered in each cell, and then buffered through two amplifiers to the outside.
You may use anything available in the standard 0.35um double-poly TSMC process, but nothing else (i.e. there is no pbase layer). Your design must pass DRC rules completely. We will be able to choose the resistor to work for your particular application. You must provide any additional bias circuitry.
The height of your cell must be less than 0.9mm. You should attempt to minimize this parameter, and I will look at this parameter in analyzing your grade for this project.
Perform a layout extraction of your file, and simulate (using EKV model) your circuit to show it meets the desired specifications. You should also check that your extraction generated by your layout tool gives you a reasonable SPICE file (i.e. no zero-length devices). Further, comment (qualitatively and quantitatively, as needed) if your circuit design is robust against typical mismatch expected in this CMOS process and how you would expect it would effect performance.