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E
d
u
c
a
t
i
o
n
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Georgia
Institute of Technology,
Atlanta, GA
PhD candidate in Electrical Eng. (GPA = 3.92/4)
Research Area: Device and Interconnection modeling
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2001-present
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Georgia
Institute of Technology,
Atlanta, GA
MS in Electrical Eng. (GPA = 4/4).
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2001-2002
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Sharif
University of Technology,
Tehran, Iran
MS in Electronics. (GPA = 17.67/20).
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1996-1998
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Sharif
University of Technology,
Tehran, Iran
BS in Electronics. (GPA = 18.08/20, second top student in the class)
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1992-1994
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E
x
p
e
r
i
e
n
c
e
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T
e
a
c
h
i
n
g
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Sharif
University
of Technology, Tehran, Iran
Teaching assistant in several courses: "Physics I" (Physics Dept.),
"Electronics II", "Electrical Circuits II", "Solid State Electronic
Devices", "Electronic Labs
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1993-1998
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AMRC
(Advance
Manufacturing Research Center), Tehran, Iran
Selecting and editing lecture notes on "Robotics"
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1995-1996
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Sadjad
Higher
Education Institute, Mashad, Iran
Teaching the course of "Electronics II"
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1999-2000
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I
n
d
u
s
t
r
i
a
l
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AMRC,
Tehran, Iran
Cooperation in constructing a "Robot Controller with 5 degree's of
freedom"
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1995-1996
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AMRC,
Tehran, Iran
Design and construction of 1kw switching power supply for driving DC
motors of a robot
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1996-1997
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A
c
a
d
e
m
i
c
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Sharif
University
of Technology, Tehran, Iran
Constructing internal interfacing cards on PC for an "Airplane
Simulator" at Aerospace Lab; Mechanical Dept.
Cooperation in "Finger Print Recognition" project (supported by the
office of Vice president for research)
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1996-1997
1995-1996
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Georgia
Institute of
Technology, Atlanta, GA
Graduate Research assistant, Microelectronic Research Center, GigaScale
Integration Group
• Random dopant fluctuation modeling
• Study of “Anomalous Skin Effect” for GSI
Interconnect
• Compact physical models for delay and bit-rate limit of GSI
wires
• Impact of size effect on multi-layer interconnect
network
• Comparison between carbon nanotube and copper interconnects
as interconnects for GSI applications
• Global power distribution network
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2000-2001
2002-present
2003-present
2004-present
2004-present
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C
o S
m k
p i
u l
t l
e s
r
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Languages:
C/C++, HTML, VHDL, Verilog HDL, 8086 Assembly
Math Tools:
Matlab, Femlab, Mathematica, Maple
Design Tools:
HSpice, Cadence, Synopsys Raphael
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H
o
n
o
r
s
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XXIII
International Physics
Olympiad, Finland
Member of Iranian Team in 23rd International Physics Olympiad
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1992
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First
National Student Olympiad,
Uromia, Iran
6th place in the first University National Olympiad
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1996
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P
u
b
l
i
c
a
t
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o
n
s
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Reza Sarvari, Azad Naeemi, Raguraman Venkatesan, and James D.
Meindl, “Impact of size effects in copper wires on design and
performance of multi-level interconnect network,” to be
submitted to IEEE Transactions of Electron Devices.
C. Sekar, Azad Naeemi, Jeffrey A. Davis, Reza Sarvari, James D. Meindl,
“Intsim: a CAD tool for optimization of multilevel
interconnect networks,” ICCAD 2007 , pp 560 - 567.
Bakir, M. S., Dang, B., Ogunsola, O. O. A., Sarvari, R., and Meindl, J.
D., "Electrical and Optical Chip I/O Interconnections for Gigascale
Systems," IEEE Electron
Device, vol. 54, pp. 2426 - 2437, Sept. 2007
Reza Sarvari, Azad Naeemi, Payman Zarkesh-Ha and James D. Meindl,
“Design and Optimization for Nanoscale Power Distribution
Networks in Gigascale Systems,” IITC, June 2007.
Gerald Lopez,
Raghunath Murali, Reza Sarvari, Keith Bowman, Jeffrey Davis, and James
Meindl, “The Impact of Size Effects and Copper Interconnect
Process Variations on the Maximum Critical Path Delay of Single and
Multi-Core Microprocessors,” Proceedings of
IITC, June 2007.
Azad Naeemi, Reza
Sarvari and James D. Meindl, "Performance Modeling and Optimization for
Single- and Multi-Wall Carbon Nanotube Interconnects," DAC 2007, June 2007
Azad
Naeemi, Reza
Sarvari and James D. Meindl, "On-Chip Interconnect Networks at the End
of the Roadmap: Limits and Nanotechnology Opportunities," (Invited paper) Proceedings of
IITC, pp 201-203, June 2006.
Reza
Sarvari, Azad
Naeemi, Raguraman Venkatesan and James D. Meindl, “Impact of
Size Effects on the Resistivity of Copper Wires and Consequently the
Design and Performance of Metal Interconnect Networks” , Proceedings of IITC,
pp 197-199, June 2005..
Azad
Naeemi, Reza
Sarvari and James D. Meindl, "Performance Comparison Between Carbon
Nanotube and Copper interconnects for Gigascale Integration (GSI)," IEEE Electron Device Letters,
vol. 26, pp. 84–86, April 2005.
Azad
Naeemi, Reza
Sarvari and James D. Meindl, "Performance Comparison Between Carbon
Nanotube and Copper Interconnects for GSI”, IEEE IEDM Digest,
pp. 699-702, Dec. 2004.
Sarvari, R.;
Naeemi, A.; Meindl, J.D.;
"General Compact Model for Bit-Rate Limit of Electrical Interconnects
Considering DC Resistance, Skin Effect and Surface Scattering"; Proceedings
of the IEEE International Interconnect Technology Conference,
June
7-9, 2004, pp 163 - 166.
Shakeri, K.;
Sarvari, R.; Meindl, J.D.; "A
compact substrate spreading resistance model for SoC"; Proceedings
of the IEEE International Systems-on-Chip Conference, 17-20
Sept.
2003, pp 333 - 336.
Sarvari, R.;
Meindl, J.D.; "On the study
of anomalous skin effect for GSI interconnections"; Proceedings
of
the IEEE International Interconnect Technology Conference,
June
2-4, 2003, pp 42 - 44.
Sarvari, R.; "Chaos in
Electronics"; Proceeding
of second seminar on Differential Equations Dynamical Systems and their
Applications,1-3 May 1998; Isfahan; pp 34-40.
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