• Embedded Parallel Architectures for Multimedia
• Background Modeling
• Midground Object Detection
• High-Performance Color Imaging
• Engineering Education
• Dynamic Optimization of Data Communication in Multimedia Architectures
• Video-centric Applications
• Hyperspectral Processing and Data Fusion
• Parallelizing Sequential Image Processing Software
• Optoelectronic Interconnect
• Architectural Modeling
• Data Vortex Optical Interconnection Networks
• Computer Architecture, Systems, and Technology

Embedded Parallel Architectures for Multimedia

• S. Apewokin, B. Valentine, L. M. Wills and S. Wills, Cat-Tail DMA: Efficient Image Data Transport for Multicore Embedded Mobile Systems, Journal of Mobile Multimedia, Special Issue on Recent Advances in Mobile and Multimedia Applications, Vol. 6, No. 2, Rinton Press, pp. 170-184, June 2010.
• W. H. Robinson and D. S. Wills, Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture, Journal of VLSI Signal Processing, Special Issue on System-on-a-Chip for Multimedia Systems, Vol. 41, No. 1, pp. 65-80, August 2005.
• A. Gentile, S. Sander, L. M. Wills and D. S. Wills, The Impact of Grain Size on the Efficiency of Embedded SIMD Image Processing Architectures, Journal of Parallel and Distributed Computing, Vol. 64, No. 11, pp. 1318-1327, November 2004.
• A. Gentile and D. S. Wills, Portable Video Supercomputing, IEEE Transactions on Computers, Vol. 53, No. 8, pp. 960-973, August 2004.
• W. H. Robinson and D. S. Wills, Analysis of Area-time Efficiency for an Integrated Focal Plane Architecture, Proceedings for the 15^th Annual Symposium on Electronic Imaging: Science and Technology, Image and Video Communications and Processing 2003, Vol. 5022, SPIE and IS&T, pp. 272-283, Santa Clara, California, January 2003.
• W. H. Robinson, G. E. Triplett and D. S. Wills, Component Modeling for an Integrated Digital Pixel, Proceedings for the 15^th Annual Meeting of the IEEE Lasers and Electro-Optics Society, Display and Imaging Systems, pp. 37-38, Glasgow, Scotland, November 2002.
• W. H. Robinson and D. S. Wills, Design of an Integrated Focal Plane Architecture for Efficient Image Processing, Proceedings of the 15^th International Conference on Parallel and Distributed Computing Systems (PDCS2002), pp. 128-135, Louisville, Kentucky, September 2002.
• A. Gentile, D. S. Wills, J. L. Cruz-Rivera and F. Sorbello, Real-Time, Low Level Image Processing on SIMPil - an Embedded SIMD Architecture, AIIA Notizie, Proceedings of the Italian Association for Artificial Intelligence (AI*IA), Vol. 15, No. 4, pp. 40-43, Bari, Italy, also appeared in Proceedings of the Seventh Conference of the Italian Association for Artificial Intelligence (AI*IA 2001), February 2002.
• A. Gentile and D. S. Wills, Impact of Pixel per Processor Ratio on Embedded SIMD Architectures, Proceedings of the 11^th IEEE International Conference on Image Analysis and Processing (ICIAP2001), pp. 204-208, Palermo, Italy, September 2001.
• A. Gentile, D. S. Wills and F. Sorbello, A Novel Methodology for the Design of Processing Elements in Embedded SIMD Architectures for Multimedia, Proceedings of the 2001 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA2001), pp. 437-443, Las Vegas, Nevada, June 2001.
• W. H. Robinson and D. S. Wills, Cost Modeling for Early Image Processing Applications, Proceedings of the 2^nd Annual International Workshop for Digital and Computational Video, DTV, and HDTV Technology, pp. 29-34, Tampa, Florida, February 2001.
• Y. Joo, J. Park, M. Thomas, K. Chung, M. A. Brooke, N. M. Jokerst and D. S. Wills, Smart CMOS Focal Plane Arrays: A Si CMOS Detector Array and Sigma-Delta Analog-to-Digital Converter Imaging System, IEEE Journal of Special Topics in Quantum Electronics, Special Issue on Smart Photonic Components, Interconnect, Processing, Vol. 5, No. 2, pp. 296-305, March 1999.
• S. M. Chai, A. Gentile and D. S. Wills, Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor, Proceedings of the 20^th Anniversary Conference on Advanced Research in VLSI, pp. 57-71, Atlanta, Georgia, March 1999.
• W. H. Robinson, D. S. Wills, M. A. Brooke and N. M. Jokerst, IRIS: An Integrated, Scalable Focal Plane Architecture, Proceedings of LEOS'98 11^th Annual Meeting, Optical Image Processing, Memory, 3D Interconnects, pp. 184-185, Orlando, Florida, December 1998.
• S. Bond, S. Jung, O. Vendier, M. Brooke, N. M. Jokerst, S. Chai, A. Lopez-Lagunas and D. S. Wills, 3D Stacked Si CMOS VLSI Smart Pixels Using Through-Si Optoelectronic Interconnections, Proceedings of the IEEE Lasers and Electro-Optics Society Summer Topical Meeting on Smart Pixels, pp. 27-28, Monterey, California, July 1998.
• H. H. Cat, A. Gentile, J. C. Eble, M. Lee, O. Vendier, Y. J. Joo, D. S. Wills, M. Brooke, N. M. Jokerst, A. S. Brown and R. Leavitt, SIMPil: An OE Integrated SIMD Architecture for Focal Plane Processing Applications, Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections, pp. 44-52, Maui, Hawaii, October 1996.
• D. S. Wills, Smart Pixel Architectures for Image Processing, Digest of the IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels, pp. 93-94, August 1996.
• D. S. Wills, J. M. Baker, H. H. Cat, S. M. Chai, L. Codrescu, J. Cruz-Rivera, J. Eble, A. Gentile, M. Hopper, W. S. Lacy, A. Lopez-Lagunas, P. May, S. Smith and T. Taha, Processing Architectures for Smart Pixel Systems, IEEE Journal of Selected Topics in Quantum Electronics, Vol. 2, No. 1, pp. 24-34, April 1996.
• S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan H. H. Cat, S. Wilkinson, M. Lee, N. M. Jokerst and M. A. Brooke, A Three Dimensional High-Throughput Architecture Using Through-Wafer Optical Interconnect, IEEE/OSA Journal of Lightwave Technology Special Issue on Optical Interconnections for Information Processing, Vol. 13, No. 6, pp. 1085-1092, June 1995.

Background Modeling

• B. Valentine, S. Apewokin, L. M. Wills and S. Wills, An Efficient, Chromatic Clustering-Based Background Model for Embedded Vision Platforms, to appear Journal of Computer Vision and Image Understanding, Elsevier, 2010.
• S. Apewokin, B. Valentine, J. Choi, L. M. Wills and S. Wills, Real-Time Adaptive Background Modeling for Multicore Embedded Systems, Journal of Signal Processing Systems for Signal, Image, and Video Technology, Springer, online January 2009.
• S. Apewokin, B. Valentine, D. Forsthoefel, S. Wills, L. M. Wills and A. Gentile, Embedded Real-Time Surveillance Using Multimodal Mean Background Modeling, Embedded Computer Vision, B. Kisacanin and S. Bhattacharyya and S. Chai(eds.), Springer, pp. 163-175, peer-reviewed, January 2009.
• B. Valentine, J. Choi, S. Apewokin, L. M. Wills and S. Wills, Bypassing BigBackground: An Efficient Hybrid Background Modelling Algorithm for Embedded Video Surveillance, Proceedings of the Second ACM/IEEE International Conference on Distributed Smart Cameras (ICDSC-08), pp. 1-8, Stanford University, CA, September 2008.
• J. Choi, S. Apewokin, B. Valentine, S. Wills and L. M. Wills, Edge Noise Removal in Multimodal Background Modeling Techniques, Proceedings of the SPIE - Image Processing: Machine Vision Applications, Vol. 6813, No. 1, Kurt S. Niel and David Fofi(eds.), pp. 1-7, San Jose, California, March 2008.
• S. Apewokin, B. Valentine, S. Wills, L. M. Wills and A. Gentile, Multimodal Mean Adaptive Backgrounding for Embedded Real-Time Video Surveillance, Proceedings of the Embedded Computer Vision Workshop (ECVW07), pp. 1-6, Minneapolis, Minnesota, held in conjunction with the 2007 IEEE Conference on Computer Vision and Pattern Recognition (CVPR-2007), June 2007.

Midground Object Detection

• B. Valentine, S. Apewokin, L. M. Wills, S. Wills and A. Gentile, Midground Object Detection in Real World Video Scenes, Proceedings of the IEEE International Conference on Advanced Video and Signal-based Surveillance (AVSS), pp. 517-522, London, England, September 2007.

High-Performance Color Imaging

• J. Kim, L. M. Wills and S. Wills, Color-Aware Instructions for Embedded Superscalar Processors, to appear Journal of Signal Processing Systems, Springer, 2010.
• J. M. Kim, S. Wills and L. M. Wills, Implementing and Evaluating a Color-Aware Instruction Set for Low-Memory, Embedded Video Processing in Data Parallel Architectures, Proceedings of the IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2005), Lecture Notes in Computer Science, Vol. 3824, Springer-Verlag, pp. 4 - 16, Nagasaki, Japan, Best Paper Award, December 2005.
• J. M. Kim, S. Wills and L. M. Wills, Architectural Enhancements for Color Image and Video Processing on Embedded Systems, Proceedings of the 10^th Asia-Pacific Conference: Advances in Computer Systems Architecture (ACSAC 2005), Lecture Notes in Computer Science, Vol. 3740, Springer-Verlag, pp. 104 - 117, Singapore, October 2005.
• J. M. Kim, S. Wills and L. M. Wills, Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures, Proceedings of the 10^th Asia-Pacific Conference: Advances in Computer Systems Architecture (ACSAC 2005), Lecture Notes in Computer Science, Vol. 3740, Springer-Verlag, pp. 551 - 565, Singapore, October 2005.
• J. M. Kim, L. M. Wills and D. S. Wills, Effective Detection and Elimination of Impulse Noise for Reliable 4:2:0 YCbCr Signals Prior to Compression Encoding, Proceedings of the 30^th IEEE International Conference on Acoustics, Speech, Signal Processing (ICASSP '05), Vol. 2, pp. 1005-1008, Philadelphia, Pennsylvania, March 2005.
• J. M. Kim and D. S. Wills, Evaluating a 16-bit YCbCr (6:5:5) Color Representation for Low Memory, Embedded Video Processing, Proceedings of the IEEE International Conference on Consumer Electronics (ICCE '05), pp. 181-182, Las Vegas, Nevada, January 2005.
• J. M. Kim and D. S. Wills, Efficient Processing of Color Image Sequences using a Color-Aware Instruction Set on Mobile Systems, Proceedings of the 15^th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2004), pp. 137-149, Galveston, Texas, September 2004.
• J. M. Kim and D. S. Wills, Combining the Quantized Color Instruction Set and Loop Unrolling on Portable Video Processing Systems, Proceedings of 16^th SPIE-IS&T Electronic Imaging, Embedded Processors for Multimedia and Communications, Vol. 5309, pp. 80-91, San Jose, California, January 2004.
• J. M. Kim and D. S. Wills, High-Performance and Energy-Efficient Heterogeneous Subword Parallel Instructions, Proceedings of the IEEE International Workshop on Signal Processing Systems (SiPS03), pp. 75-80, Seoul, Korea, August 2003.
• J. M. Kim and D. S. Wills, Quantized Color Instruction Set for Media-On-Demand Applications, Proceedings of the IEEE International Conference on Multimedia & Expo (ICME’03), pp. 141-144, Baltimore, Maryland, July 2003.
• J. M. Kim and D. S. Wills, Evaluating Color Instruction Set Extension for Real-Time Vector Quantization, Proceedings of the IEEE CAMP 2003 International Workshop on Computer Architectures for Machine Perception, pp. 113-120, New Orleans, Louisiana, May 2003.
• J. M. Kim and D. S. Wills, Fast Color Image Processing Using Quantized Color Instruction Set, Proceedings of the IEEE International Conference on Information Technology: Coding and Computing (ITCC 2003), pp. 529-535, Las Vegas, Nevada, April 2003.

Engineering Education

• L. M. Wills and D. S. Wills, MiSaSiM: A Resource-Aware Programming Environment for Computer Systems Engineering Education, 2007 Frontiers in Education Conference (FIE07), pp. S1C:7-12, Milwaukee, Wisconsin, October 2007.
• D. S. Wills and J. A. Hughes, An Integrated Core Sequence in Digital Computation, Proceedings of 1995 Frontiers in Education 25^th Annual Conference: Engineering Education for the 21^st Century, pp. 2a6.1-2a6.4, Atlanta, Georgia, November 1995.

Dynamic Optimization of Data Communication in Multimedia Architectures

• S. Apewokin, B. Valentine, L. M. Wills and S. Wills, Cat-Tail DMA: Efficient Image Data Transport for Multicore Embedded Mobile Systems, Journal of Mobile Multimedia, Special Issue on Recent Advances in Mobile and Multimedia Applications, Vol. 6, No. 2, Rinton Press, pp. 170-184, June 2010.
• P. Sassone, S. Wills and G. Loh, Static Strands: Safely Exposing Dependence Chains for Increasing Embedded Power Efficiency, ACM Transactions on Embedded Computing Systems (TECS), Vol. 6, No. 4, pp. 24:1-26, September 2007.
• H. Kim, S. Wills and L. M. Wills, Optimizing Operand Transport using Dynamic SIMDization in Multimedia Systems, Proceedings of the IEEE International Workshop on Multimedia Signal Processing, pp. 372-377, Victoria, British Columbia, Canada, October 2006.
• H. Kim, S. Wills and L. M. Wills, Reducing Operand Communication Overhead using Instruction Clustering for Multimedia Applications, Proceedings of the 7^th IEEE International Symposium on Multimedia (ISM 2005), pp. 345-352, Irvine, California, December 2005.
• P. Sassone, S. Wills and G. Loh, Static Strands: Safely Collapsing Dependence Chains for Increasing Embedded Power Efficiency, Proceedings of the Conference on Languages, Compilers, Tools for Embedded Systems (LCTES), pp. 127-136, Chicago, Illinois, selected as one of five best papers, June 2005.
• H. Kim, D. S. Wills and L. M. Wills, Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport, Proceedings of the 4^th International Workshop on Performance Modeling, Evaluation, Optimization of Parallel and Distributed Systems (PMEO-PDS'05) , pp. 273b:1-8, Denver, Colorado, held in conjunction with the 19^th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05), April 2005.
• P. G. Sassone and D. S. Wills, Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication, Proceedings of the 37^th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 7-17, Portland, Oregon, December 2004.
• P. G. Sassone and D. S. Wills, On the Extraction and Analysis of Prevalent Dataflow Patterns, The IEEE 7^th Annual Workshop on Workload Characterization (WWC-7), 8 pages, Austin, Texas, October 2004.
• H. Kim, D. S. Wills and L. M. Wills, Empirical Analysis of Operand Usage and Transport in Multimedia Applications, Proceedings of the 4^th IEEE International Workshop on System-on-Chip for Real-Time Applications(IWSOC’04), pp. 168-171, Banff, Alberta, Canada, July 2004.
• P. G. Sassone and D. S. Wills, Multicycle Broadcast Bypass: Too Readily Overlooked, Proceedings of the Workshop on Complexity Effective Design (WCED), 5 pages, Munich, Germany, June 2004.
• S. Bunchua, D. S. Wills and L. M. Wills, Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files, Proceedings of the International Conference on Computer Design (ICCD), pp. 532-535, San Jose, California, October 2003.

Video-centric Applications

• S. Apewokin, B. Valentine, R. Bales, L. M. Wills and S. Wills, Tracking Multiple Pedestrians in Real-Time Using Kinematics, Proceedings of the Embedded Computer Vision Workshop (ECVW08), pp. 1-6, Anchorage, Alaska, held in conjunction with the 2008 IEEE Conference on Computer Vision and Pattern Recognition (CVPR-2008), June 2008.
• J. M. Kim, L. M. Wills and D. S. Wills, Effective Detection and Elimination of Impulse Noise for Reliable 4:2:0 YCbCr Signals Prior to Compression Encoding, Proceedings of the 30^th IEEE International Conference on Acoustics, Speech, Signal Processing (ICASSP '05), Vol. 2, pp. 1005-1008, Philadelphia, Pennsylvania, March 2005.
• A. Gentile, S. Sander, L. M. Wills and D. S. Wills, The Impact of Grain Size on the Efficiency of Embedded SIMD Image Processing Architectures, Journal of Parallel and Distributed Computing, Vol. 64, No. 11, pp. 1318-1327, November 2004.
• A. Gentile and D. S. Wills, Portable Video Supercomputing, IEEE Transactions on Computers, Vol. 53, No. 8, pp. 960-973, August 2004.
• J. M. Kim and D. S. Wills, Fast Vector Median Filter Implementation Using the Color Pack Instruction Set, Proceedings of the 10^th IEEE Digital Signal Processing Workshop, pp. 339-343, Pine Mountain, Georgia, October 2002.
• J. M. Kim, S. Ryu, A. Gentile, L. M. Wills and D. S. Wills, Impulse Noise Removal on an Embedded, Low Memory SIMD Processor, Proceedings of the 14^th IEEE International Conference on Digital Signal Processing (DSP2002), pp. 1257-1260, Santorini, Greece, July 2002.
• A. Gentile, J. L. Cruz-Rivera, D. S. Wills, L. Bustelo, J. J. Figueroa, J. E. Fonseca-Camacho, W. E. Lugo-Beauchamp, R. Olivieri, M. Quiñones-Cerpa, A. H. Rivera-Ríos, I. Vargas-Gonzáles and M. Viera-Vera, Real-Time Image Processing on a Focal Plane SIMD Array, Proceedings of the Seventh International Workshop on Parallel and Distributed Real-Time Systems, pp. 400-405, San Juan, Puerto Rico, April 1999.
• D. S. Wills, H. Cat, J. Cruz-Rivera, W. S. Lacy, M. Baker, J. Eble, A. Lopez-Lagunas and M. Hopper, High-Throughput, Low-Memory Applications on the Pica Architecture, IEEE Transactions on Parallel and Distributed Systems, Vol. 8, No. 10, pp. 1055-1067, October 1997.
• Y. Joo, S. Fike, K. S. Chung, M. A. Brooke, N. M. Jokerst and D. S. Wills, Application of Massively Parallel Processors to Real Time Processing of High Speed Images, Proceedings of the Fourth International Conference on Massively Parallel Processing Using Optical Interconnections, pp. 96-100, Montreal, Canada, June 1997.
• A. Gentile, H. Cat, F. Kossentini, F. Sorbello and D. S. Wills, Real-Time Vector Quantization-Based Image Compression on the SIMPil Low Memory SIMD Architecture, Proceedings of the IEEE International Performance, Computing, Communications Conference, pp. 10-16, Phoenix, Arizona, Best Paper Award, February 1997.
• J. L. Cruz-Rivera, E. V. R. DiBella, D. S. Wills, T. K. Gaylord and E. N. Glytsis, Parallelized Formulation of the Maximum Likelihood-Expectation Maximization Algorithm for Fine-Grain Message-Passing Architectures, IEEE Transactions on Medical Imaging, Vol. 14, No. 4, pp. 758-762, December 1995.
• S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan H. H. Cat, S. Wilkinson, M. Lee, N. M. Jokerst and M. A. Brooke, A Three Dimensional High-Throughput Architecture Using Through-Wafer Optical Interconnect, IEEE/OSA Journal of Lightwave Technology Special Issue on Optical Interconnections for Information Processing, Vol. 13, No. 6, pp. 1085-1092, June 1995.

Hyperspectral Processing and Data Fusion

• S. M. Chai, A. Gentile, W. E. Lugo-Beauchamp, J. Fonseca, J. L. Cruz-Rivera and D. S. Wills, Focal Plane Processing Architectures for Real-time Hyperspectral Image Processing, Applied Optics, Special Issue on Optics in Computing, Vol. 39, No. 5, pp. 835-849, February 2000.
• M. Chai, A. Gentile, W. E. Lugo-Beauchamp, J. L. Cruz-Rivera and D. S. Wills, Hyper-spectral Image Processing Applications on the SIMD Pixel Processor for the Digital Battlefield, Proceedings of the IEEE Workshop on Computer Vision Beyond the Visible Spectrum: Methods and Applications, pp. 130-138, Fort Collins, Colorado, June 1999.

Parallelizing Sequential Image Processing Software

• L. M. Wills, T. Taha, L. Baumstark and S. Wills, Estimating Potential Parallelism for Platform Retargeting, Proceedings of the 9^th Working Conference on Reverse Engineering (WCRE), IEEE Computer Society Press, pp. 55-64, Richmond, Virginia, October 2002.

Optoelectronic Interconnect

• C. Hawkins, D. S. Wills, O. Liboiron-Ladouceur and K. Bergman, Hierarchical Clustering of the Data Vortex Optical Interconnection Network, OSA Journal of Optical Networking, Vol. 6, No. 9, pp. 1179-1190, September 2007.
• C. Hawkins, B. A. Small, D. S. Wills and K. Bergman, The Data Vortex, an All Optical Path Multicomputer Interconnection Network, IEEE Transactions of Parallel and Distributed Systems, Vol. 18, No. 3, pp. 409-420, March 2007.
• C. Hawkins and S. Wills, Impact of Number of Angles on the Performance of the Data Vortex Optical Interconnection Network, IEEE Journal of Lightwave Technology, Vol. 24, No. 9, pp. 3288-3294, September 2006.
• B. A. Small, A. Shacham, K. Bergman, K. Athikulwongse, C. Hawkins and D. S. Wills, Emulation of Realistic Network Traffic Patterns on an Eight-Node Data Vortex Interconnection Network Subsystem, OSA Journal of Optical Networking, Vol. 3, No. 11, pp. 802-809, November 2004.
• N. M. Jokerst, M. A. Brooke, J. Laskar, D. S. Wills, A. S. Brown, M. Vrazel, S. Jung, Y. Joo and J. J. Chang, Microsystem Optoelectronic Integration for Mixed Multisignal Systems, IEEE Journal on Selected Topics in Quantum Electronics, Vol. 6, No. 6, pp. 1231-1239, November 2000.
• A. Lopez-Lagunas, S. M. Chai, J. Cross, B. Buchanan, L. Carastro, S. Wang, D. S. Wills, N. M. Jokerst, M. A. Brooke and M. A. Ingram, Bi-Directional Single Fiber Optoelectronic Interconnect for Automotive Applications, IEEE Transactions on Vehicular Technology, Vol. 49, No. 1, pp. 281-287, January 2000.
• N. M. Jokerst, M. A. Brooke, J. Laskar, D. S. Wills, A. S. Brown, V. Olivier, S. Bond, J. Cross, M. Vrazel, M. Thomas, M. Lee, S. Jung, Y. J. Joo and J. J. Chang, Smart Photonics: Optoelectronics Integrated onto Si CMOS Circuits, Proceedings of the 1999 12^th Annual Meeting IEEE Lasers and Electro-Optics Society (LEOS'99), pp. 423-424, San Francisco, California, November 1999.
• J. Park, J. A. Tabler, M. A. Brooke, N. M. Jokerst and D. S. Wills, Adaptive Digital Bias Control for an Optical Receiver and Transmitter, Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, pp. I-323 - I-326, Orlando, Florida, May 1999.
• J. J. Chang, M. Lee, S. Jung, M. A. Brooke, N. M. Jokerst and D. S. Wills, Fully Differential Current-input CMOS Amplifier Front-end Suppressing Mixed Signal Substrate Noise for Optoelectronic Applications, Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, pp. I-327 - I-330, Orlando, Florida, May 1999.
• S. Bond, O. Vendier, M. Lee, S. Jung, A. Lopez-Lagunas, S. Chai, G. Dagnall, M. Brooke, N. Jokerst, D. S. Wills and A. Brown, A Three-Layer 3-D Silicon System Using Through-Si Vertical Optical Interconnections and Si CMOS Hybrid Building Blocks, IEEE Journal of Special Topics in Quantum Electronics, Special Issue on Smart Photonic Components, Interconnect, Processing, Vol. 5, No. 2, pp. 276-286, March 1999.
• Y. Joo, J. Park, M. Thomas, K. Chung, M. A. Brooke, N. M. Jokerst and D. S. Wills, Smart CMOS Focal Plane Arrays: A Si CMOS Detector Array and Sigma-Delta Analog-to-Digital Converter Imaging System, IEEE Journal of Special Topics in Quantum Electronics, Special Issue on Smart Photonic Components, Interconnect, Processing, Vol. 5, No. 2, pp. 296-305, March 1999.
• M. A. Brooke, N. M. Jokerst, S. W. Bond and D. S. Wills, A Comparison of CMOS Chip to Chip Interconnections: Vertical Optical Through-Si Links Versus High Density Electrical Interconnect, Proceedings of LEOS'98 11^th Annual Meeting, Optical Image Processing, Memory, 3D Interconnects, pp. 186-187, Orlando, Florida, December 1998.
• Y. Joo, M. Thomas, S. Fike, K. Chung, M. Brooke, N. M. Jokerst and D. S. Wills, High Speed, Smart Focal Plane Processing Using Integrated Photodetectors, Si CMOS VLSI Sigma Delta Analog to Digital Converters, Proceedings of the IEEE Lasers and Electro-Optics Society Summer Topical Meeting on Smart Pixels, pp. 55-56, Monterey, California, July 1998.
• J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord and E. N. Glytsis, Optimal Usage of the Available Wiring Resources in Diffractive-Reflective Optoelectronic Multichip Modules, Applied Optics, Special Issue on Massively Parallel Optical Interconnections for High Performance Computing, Vol. 37, No. 2, pp. 233-253, January 1998.
• S. M. Chai, A. Lopez-Lagunas, D. S. Wills, N. M. Jokerst and M. A. Brooke, Systolic Processing Architectures Using Optoelectronic Interconnects, Proceedings of the Fourth International Conference on Massively Parallel Processing Using Optical Interconnections, pp. 160-166, Montreal, Canada, June 1997.
• Y. Joo, S. Fike, K. S. Chung, M. A. Brooke, N. M. Jokerst and D. S. Wills, Application of Massively Parallel Processors to Real Time Processing of High Speed Images, Proceedings of the Fourth International Conference on Massively Parallel Processing Using Optical Interconnections, pp. 96-100, Montreal, Canada, June 1997.
• P. May, J. Cross, A. Lopez-Lagunas, B. Buchanan, D. S. Wills, N. M. Jokerst and M. Brooke, Improvement in Bit Error Rate for Optoelectronic Multicomputer Interconnection Networks Using Cyclic Redundancy Code Error Detection, IEEE Photonics Technology Letters, Vol. 9, No. 6, pp. 848-850, June 1997.
• S. C. Wang, J. Cross, S. M. Chai, A. Lopez, J. Park, M. A. Ingram, N. M. Jokerst, D. S. Wills, M. Brooke and A. Brown, Coupling Efficiency of an Alignment-Tolerant, Single Fiber, Bi-Directional Link, Proceedings of the 47^th Electronic Components and Technology Conference, pp. 30-36, San Jose, California, May 1997.
• P. May, M. Lee, S. Wilkinson, O. Vendier, Z. Ho, S. Bond, D. S. Wills, M. A. Brooke, N. M. Jokerst and A. Brown, A 100 Mbps, LED Through-Wafer Optoelectronic Link for Multicomputer Interconnection Networks, Journal of Parallel and Distributed Computing, Special Issue on Parallel Computing with Optical Interconnects, Vol. 41, No. 1, pp. 3-19, February 1997.
• J. Cross, A. Lopez-Lagunas, B. Buchanan, L. Carastro, S. Wang, N. M. Jokerst, D. S. Wills, M. Brooke and M. A. Ingram, A Single-Fiber Bidirectional Optical Link Using Colocated Emitters and Detectors, IEEE Photonics Technology Letters, Vol. 8, No. 10, pp. 1385-1387, October 1996.
• J. Cross, A. Lopez-Lagunas, B. Buchanan, L. Carastro, S. C. Wang, N. M. Jokerst, D. S. Wills, M. Brooke and M. A. Ingram, A Smart Pixel Bi-Directional Optical Link Using Co-Located Emitters and Detectors, Digest of the IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels, pp. 74-77, August 1996.
• M. Brooke, S. Wills, N. Jokerst, A. Brown, M. Ingram, R. Bicknell-Tassius, J. Cross, S. Chai, A. Lopez and J. Park, Low Cost Alignment Tolerant Plastic Fiber Optic Interconnect, Workshop on Fiber Optics for Missile Applications, 4 pages, Huntsville, Alabama, May 1996.
• H. H. Cat, J. C. Eble, D. S. Wills, V. K. De, M. Brooke and N. M. Jokerst, Low Power Opportunities for a SIMD VLSI Architecture Incorporating Integrated Optoelectronic Devices, Proceedings of the Government Microelectronics Applications Conference (GOMAC’96), pp. 59-62, Orlando, Florida, March 1996.
• N. M. Jokerst, M. A. Brooke, O. Vendier, S. Wilkinson, S. Fike, M. Lee, E. Twyford, J. Cross, B. Buchanan and D. S. Wills, Thin Film Multi-Material Optoelectronic Integrated Circuits, IEEE Transactions on Components, Packaging, Manufacturing Technology Part B: Advanced Packaging, Vol. 19, No. 1, pp. 97-106, February 1996.
• N. M. Jokerst, M. A. Brooke, O. Vendier, S. Wilkinson, S. Fike, M. Lee, B. Buchanan, D. S. Wills and A. Brown, Manufacturable Multi-Material Integration: Compound Semiconductor Devices Bonded to Silicon Circuitry, Proceedings of the Defense Manufacturing Conference, 1005 pages, Dallas, Texas, November 1995.
• P. May, S. Wilkinson, N. M. Jokerst, D. S. Wills, M. Lee, O. Vendier, S. W. Bond, Z. Ho, G. Dagnall, M. A. Brooke and A. Brown, Design Issues for Through-Wafer Optoelectronic Multicomputer Interconnects, Proceedings of the Second International Conference on Massively Parallel Processing Using Optical Interconnections, pp. 8-15, San Antonio, Texas, October 1995.
• N. M. Jokerst, M. A. Brooke, O. Vendier, S. Wilkinson, S. Fike, M. Lee, B. Buchanan, D. S. Wills and A. S. Brown, Manufacturable Multimaterial Integration: Compound Semiconductor Devices Bonded to Silicon Circuitry, Proceedings of the SPIE National Science Foundation (NSF) Forum on Optical Science and Engineering, Vol. 2524, pp. 153-164, Alexandria, Virginia, September 1995.
• N. M. Jokerst, M. A. Brooke, O. Vendier, M. Lee, S. Fike, B. Buchanan and D. S. Wills, Smart Detectors: Devices, Integration, Circuits, Systems, Proceedings of the Society of Photo Instrumentation Engineering Annual Meeting, Vol. 2550, pp. 212-223, San Diego, California, July 1995.
• S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan H. H. Cat, S. Wilkinson, M. Lee, N. M. Jokerst and M. A. Brooke, A Three Dimensional High-Throughput Architecture Using Through-Wafer Optical Interconnect, IEEE/OSA Journal of Lightwave Technology Special Issue on Optical Interconnections for Information Processing, Vol. 13, No. 6, pp. 1085-1092, June 1995.
• H. Cat, D. S. Wills, N. M. Jokerst, M. A. Brooke and A. Brown, Three Dimensional, Massively Parallel, Optically Interconnected Silicon Computational Hardware and Architectures for High Speed IR Scene Generation, Proceedings of the 1995 SPIE Symposium on OE/ Aerospace Sensing and Dual Use Photonics: Targets and Backgrounds: Characterization and Representation, Vol. 2469, pp. 141-145, Orlando, Florida, April 1995.
• H. H. Cat, M. Lee, B. Buchanan, D. S. Wills, M. A. Brooke and N. M. Jokerst, Silicon VLSI Processing Architectures Incorporating Integrated Optoelectronic Devices, Proceedings of the 16^th Conference on Advanced Research in VLSI, pp. 17-27, Chapel Hill, North Carolina, March 1995.
• S. Wills, N. M. Jokerst, M. A. Brooke and A. Brown, A Two Layer Image Processing System Incorporating Integrated Focal Plane Detectors and Through-Wafer Optical Interconnect, Technical Digest of the 1995 OSA Optical Computing Topical Meeting, pp. 19-22, Salt Lake City, Utah, March 1995.
• S. Wills, N. M. Jokerst and M. Brooke, Manufacturable Digital Processing Systems Incorporating Integrated Thin-Film Devices, Conference on Manufacturing Process Development in Photonics, pp. 29-34, Huntsville, Alabama, November 1994.
• N. M. Jokerst, M. Brooke, M. Allen and D. S. Wills, Manufacturable Multi-Material Integrated Systems, Conference on Manufacturing Process Development in Photonics, pp. 225-227, Huntsville, Alabama, November 1994.
• D. S. Wills, W. S. Lacy and J. L. Cruz-Rivera, The Offset Cube: An Optoelectronic Interconnection Network, Proceedings of the PCRCW, Parallel Computer Routing and Communication, Lecture Notes in Computer Science, Vol. 853, K. Bolding and L. Snyder(eds.), pp. 86-100, Seattle, Washington, May 1994.
• W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, D. S. Wills, N. M. Jokerst and M. A. Brooke, A Fine-Grain, High-Throughput Architecture Using Through-Wafer Optical Interconnect, Proceedings of the Eight International Parallel Processing Symposium: Massively Parallel Processing Using Optical Interconnect, pp. 27-36, Cancun, Mexico, April 1994.
• D. S. Wills and M. A. Grossglauser, A Scalable Optical Interconnection Network for Fine-Grain Parallel Architectures, 1993 International Conference on Parallel Processing, pp. I-154 - I-157, St. Charles, Illinois, August 1993.
• D. S. Wills and M. A. Grossglauser, A Three-Dimensional Optical Interconnection Network for Fine-Grain Parallel Architectures, Proceedings of the IEEE Lasers and Electro-Optics Summer Topical Meeting on Hybrid Optoelectric Integration and Packaging, pp. 21-22, Santa Barbara, California, July 1993.

Architectural Modeling

• T. Taha and D. S. Wills, An Instruction Throughput Model of Superscalar Processors, IEEE Transactions on Computers, Vol. 57, No. 3, pp. 389-403, March 2008.
• L. Codrescu, S. P. Nugent, J. D. Meindl and D. S. Wills, Modeling Technology Impact on Cluster Microprocessor Performance, IEEE Transactions on VLSI Systems, Vol. 11, No. 5, pp. 909-920, October 2003.
• T. Taha and D. S. Wills, An Instruction Throughput Model of Superscalar Processors, Proceedings of the 14^th IEEE International Workshop on Rapid Systems Prototyping (RSP03), pp. 156-163, San Diego, California, June 2003.
• S. P. Nugent, D. S. Wills and J. D. Meindl, A Hierarchical Block-based Modeling Methodology for SoC in GENESYS, Proceedings of the 15^th IEEE International ASIC/SoC Conference (ASIC2002), pp. 239-243, Rochester, New York, September 2002.
• M. Deb-Pant, P. Pant and D. S. Wills, On-Chip Decoupling Capacitor Optimization using Architectural Level Prediction, IEEE Transactions on VLSI, Vol. 10, No. 3, pp. 319-326, June 2002.
• S. M. Chai, T. M. Taha, D. S. Wills and J. D. Meindl, Heterogeneous Architecture Models for Interconnect-Motivated System Design, IEEE Transactions on VLSI Systems, Special Issue on System Level Interconnect Prediction, Vol. 8, No. 6, pp. 660-670, December 2000.
• J. C. Eble, S. P. Nugent, J. D. Meindl and D. S. Wills, An Ultra-Compact Empirical Model for Throughput Projection for Gigascale Integration, Proceedings of Semiconductor Research Corporation Techcon 2000, pp. 1-4, Phoenix, Arizona, Best in Session Award, September 2000.
• S. M. Chai, A. Gentile and D. S. Wills, Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor, Proceedings of the 20^th Anniversary Conference on Advanced Research in VLSI, pp. 57-71, Atlanta, Georgia, March 1999.
• L. Codrescu, M. Deb-Pant, T. Taha, J. Eble, D. S. Wills and J. Meindl, Exploring Microprocessor Architectures for Gigascale Integration, Proceedings of the 20^th Anniversary Conference on Advanced Research in VLSI, pp. 242-255, Atlanta, Georgia, March 1999.
• L. Codrescu and D. S. Wills, Profiling for Input Predictable Threads, Proceedings of the 1998 International Conference on Computer Design, VLSI in Computers & Processors (ICCD’98), pp. 558-565, Austin, Texas, October 1998.
• J. C. Eble, V. K. De, D. S. Wills and J. D. Meindl, Minimum Repeater Count, Size, Energy Dissipation for Gigascale Integration (GSI) Interconnects, Proceedings of the International Interconnect Technology Conference, pp. 56-58, San Francisco, California, June 1998.
• V. Garg, D. Schimmel, D. Stogner, C. Ulmer, D. S. Wills and S. Yalamanchili, Early Analysis of Cost/Performance Trade-Offs in MCM Systems, IEEE Transactions on Components, Packaging, Manufacturing Technology, Vol. 20, No. 3, pp. 308-319, August 1997.
• J. D. Meindl, V. K. De, D. S. Wills, J. C. Eble, X. Tang, J. Davis, B. Austin and A. J. Bhavnagarwala, Impact of Stochastic Dopant and Interconnect Distributions on Gigascale Integration, Proceedings of the 1997 IEEE International Solid-State Circuits Conference, Vol. 40, pp. 232-233, 463, San Francisco, California, February 1997.
• J. Cruz-Rivera, D. S. Wills, T. Gaylord and E. Glytsis, Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection Network, Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers & Processors (ICCD’96), pp. 165-169, Austin, Texas, October 1996.
• J. Cruz-Rivera, D. S. Wills, T. Gaylord and E. Glytsis, Performance Modeling of Optical Interconnection Technologies for Massively Parallel Processing Systems, Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections, pp. 264-275, Maui, Hawaii, October 1996.
• V. Garg, D. Schimmel, D. Stogner, C. Ulmer, D. S. Wills and S. Yalamanchili, Early Analysis of Cost/Performance Trade-Offs in MCM Systems, Proceedings of Eighth IEEE International Conference: Innovative Systems In Silicon, pp. 228-237, Austin, Texas, October 1996.
• J. C. Eble, V. K. De, D. S. Wills and J. D. Meindl, A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001, Proceedings of the Ninth Annual IEEE International ASIC Conference, pp. 193-196, Rochester, New York, Best Paper Award, September 1996.
• J. C. Eble, V. K. De, J. Davis, D. S. Wills and J. D. Meindl, A Generic System Simulator (GENESYS) for Optimal Multilevel Interconnect Technologies for Gigascale Integration (GSI), Semiconductor Research Corporation Technical Conference, TECHCON ‘96, pp. 193-196, Phoenix, Arizona, September 1996.
• V. K. De, J. C. Eble, D. S. Wills, J. Davis and J. D. Meindl, A Generic System Simulator (GENESYS) for Microelectronics Technology and Applications, Proceedings of the Government Microelectronics Applications Conference (GOMAC’96), pp. 439-442, Orlando, Florida, March 1996.

Data Vortex Optical Interconnection Networks

• C. Hawkins, D. S. Wills, O. Liboiron-Ladouceur and K. Bergman, Hierarchical Clustering of the Data Vortex Optical Interconnection Network, OSA Journal of Optical Networking, Vol. 6, No. 9, pp. 1179-1190, September 2007.
• C. Hawkins, B. A. Small, D. S. Wills and K. Bergman, The Data Vortex, an All Optical Path Multicomputer Interconnection Network, IEEE Transactions of Parallel and Distributed Systems, Vol. 18, No. 3, pp. 409-420, March 2007.
• C. Hawkins and S. Wills, Impact of Number of Angles on the Performance of the Data Vortex Optical Interconnection Network, IEEE Journal of Lightwave Technology, Vol. 24, No. 9, pp. 3288-3294, September 2006.
• B. A. Small, A. Shacham, K. Bergman, K. Athikulwongse, C. Hawkins and D. S. Wills, Emulation of Realistic Network Traffic Patterns on an Eight-Node Data Vortex Interconnection Network Subsystem, OSA Journal of Optical Networking, Vol. 3, No. 11, pp. 802-809, November 2004.

Computer Architecture, Systems, and Technology

• P. G. Sassone and D. S. Wills, On the Scaling of the Atlas Chip-Scale Multiprocessor, IEEE Transactions on Computers, Vol. 54, No. 1, pp. 82-87, January 2005.
• A. Gentile and D. S. Wills, Portable Video Supercomputing, IEEE Transactions on Computers, Vol. 53, No. 8, pp. 960-973, August 2004.
• P. May, S. Bunchua and D. S. Wills, HiPER, A Compact Narrow Channel Router with Hop-by-Hop Error Correction, IEEE Transactions on Parallel and Distributed Systems, Vol. 13, No. 5, pp. 485-498, May 2002.
• S. M. Chai and D. S. Wills, Systolic Opportunities for Multidimensional Data Streams, IEEE Transactions on Parallel and Distributed Systems, Vol. 13, No. 4, pp. 388-398, April 2002.
• L. Codrescu, D. S. Wills and J. Meindl, Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications, IEEE Transactions on Computers, Vol. 50, No. 1, pp. 67-82, January 2001.
• L. Codrescu and D. S. Wills, On Dynamic Speculative Thread Partitioning and the MEM-slicing Algorithm, Journal of Universal Computer Science, Special Issue on Multithreaded Processors and Chip-Multiprocessors, Vol. 6, No. 10, pp. 908-927, September 2000.
• M. Deb-Pant, P. Pant and D. S. Wills, On-Chip Decoupling Capacitor Optimization Using Architectural Level Current Signature Prediction, Proceedings of the 13^th Annual IEEE International ASIC/SOC Conference, pp. 288-292, Arlington, Virginia, September 2000.
• M. Deb-Pant, P. Pant, D. S. Wills and V. Tiwari, Inductive Noise Reduction at the Architectural Level, Proceedings of the 13^th International Conference on VLSI Design (VLSI DESIGN 2000), pp. 162-167, Calcutta, India, January 2000.
• L. Codrescu and D. S. Wills, On Dynamic Speculative Thread Partitioning and the MEM-slicing Algorithm, Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT’99), pp. 40-46, Newport Beach, California, October 1999.
• L. Codrescu and D. S. Wills, Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications, Proceedings of the 1999 International Conference on Computer Design, VLSI in Computers & Processors (ICCD’99), pp. 428-435, Austin, Texas, October 1999.
• W. S. Lacy, J. Cruz-Rivera and D. S. Wills, The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics, IEEE Transactions on Parallel and Distributed Systems, Vol. 9, No. 9, pp. 893-908, September 1998.
• W. Dally, A. Chang, A. Chien, S. Fiske, W. Horwat, J. Keen, R. Lethin, P. Nuth, E. Spertus, D. Wallach and D. S. Wills, The J-Machine, 25 Years of the International Symposium on Computer Architecture, Gurindar Sohi(eds.), pp. 54-58, September 1998.
• P. May, S. M. Chai and D. S. Wills, HiPER-P - An Efficient High-Performance Router for Multicomputer Interconnection Networks, Proceedings of the Parallel Computer Routing and Communications Workshop, pp. 103-116, Atlanta, Georgia, June 1997.
• O. Vendier, S. T. Wilkinson, S. W. Bond, M. L. Lee, Z. Hou, A. Lopez-Lagunas, P. May, M. Brooke, N. M. Jokerst, D. S. Wills and R. P. Leavitt, A 155 Mbps Digital Transmitter Using GaAs Thin Film LEDs Bonded to Silicon Driver Circuits, Digest of the IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels, pp. 15-16, August 1996.
• W. Appelbe, R. Harmon, P. May, D. S. Wills and M. Vitale, Hoisting Branch Conditions - Improving Super-Scalar Processor Performance, Proceedings of the Eighth International Workshop on Languages and Compilers for Parallel Computing, pp. 20.1 - 20.14, Columbus, Ohio, August 1995.
• D. S. Wills, W. S. Lacy, H. Cat, M. Hopper, A. Razdan and S. M. Chai, Pica: An Ultra-Light Processor for High-Throughput Applications, Proceedings of the 1993 International Conference on Computer Design, VLSI in Computers & Processors (ICCD’93), pp. 410-414, Cambridge, Massachusetts, October 1993.
• W. J. Dally, A. Chien, R. Davison, S. Fiske, S. Furman, G. Flyer, D. Gaunce, W. Horwat, S. Kaneshiro, J. Keen, R. Lethen, M. Noakes, P. Nuth, E. Spertus, B. Totty, D. Wallach and D. S. Wills, The J-Machine: A Fine-Grain Parallel Computer, Computing Systems in Engineering, Vol. 3, No. 1-4, pp. 7-15, December 1992.
• D. S. Wills, Processor Grain Size and Overhead for Massive Parallelism, Proceedings of the New Frontiers, IEEE Computer Society Press, pp. 79-84, October 1992.
• D. S. Wills and W. J. Dally, Pi: A Parallel Architecture Interface, The Fourth Symposium on the Frontiers of Massively Parallel Computation, pp. 345-352, McLean, Virginia, October 1992.
• W. Dally, A. Chien, J. S. Fiske, G. Fyler, W. Horwat, J. Keen, R. Lethin, M. Noakes, P. Nuth and S. Wills, The Message Driven Processor: An Integrated Processing Element, Proceedings of the 1992 International Conference on Computer Design, VLSI in Computers & Processors (ICCD’92), pp. 416-419, Cambridge, Massachusetts, October 1992.
• W. Dally, S. Ahmed, P. Carrick, A. Chien, R. Davison, S. Fiske, G. Fyler W. Horwat, J. Keen, S. Lear, R. Lethin, M. Vestrich, T. Nguyen, M. Noakes, P. Nuth and S. Wills, Design and Implementation of the Message-Driven Processor, Proceedings of the Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, pp. 5-25, Providence, Rhode Island, March 1992.
• W. J. Dally, D. S. Wills and R. Lethin, Mechanisms for Parallel Computing, Proceedings of the NATO Advanced Study Institute on Parallel Computing on Distributed Memory Multiprocessors, Springer, Ankara, Turkey, July 1991.
• D. S. Wills, Pi: A Parallel Architecture Interface for Multi-Model Execution, MIT Artificial Intelligence Laboratory Technical Report 1245, 200 pages, July 1990.
• W. J. Dally and D. S. Wills, Universal Mechanisms for Concurrency, PARLE ‘89, Lecture Notes in Computer Science, Vol. I, pp. 19-33, Eindhoven, The Netherlands, June 1989.
• T. L. Sterling, D. S. Wills and E. Y. Chan, Tokenless Static Data Flow Using Associative Templates, Proceedings of Supercomputing ‘88, pp. 70-79, Kissimmee, Florida, November 1988.
• W. Dally, L. Chao, A. Chien, S. Hassoun, W. Horwat, J. Kaplan, P. Song, B. Totty and S. Wills, Architecture of a Message-Driven Processor, Proceedings of the 14^th International Symposium on Computer Architecture, pp. 54-58, Pittsburgh, Pennsylvania, reprinted in 25 Years of the International Symposia on Computer Architecture, ed. Gurindar Sohi, September 1998, June 1987.
• D. S. Wills, Ultra-fine Grain Processing Architectures, VLSI Memo 85-245, MIT Microsystems Technology Laboratory, 120 pages, Cambridge, Massachusetts, May 1985.