Sudhakar
Yalamanchili
Professor
The School of
Electrical and Computer Engineering
Georgia Institute of Technology
Mailing Address:
Phone: (404) 894-2940
Fax: (404) 385 1746
Office: KACB 2316
Email: sudha@ece.gatech.edu
Scheduled Weekly Meetings:
Spring 2008 (TBD)
Teaching (Fall 2008): ECE 2030 : Introduction to Computer Engineering
Sudhakar Yalamanchili received the B.E degree in Electronics from Bangalore
University, India in 1978, and the MS. and Ph.D
degrees in Electrical and Computer Engineering from the University of Texas at
Austin in 1980 and 1984 respectively.
He is currently a Professor in the School of Electrical and Computer
Engineering at the Georgia Institute of Technology in Atlanta GA. Prior to
joining Georgia Tech in 1989 he was Senior and then Principal Research
Scientist at the Honeywell Systems and Research Center in Minneapolis from 1984
to 1989. At Honeywell he was the Principal Investigator for projects in the
design and analysis of multiprocessor architectures for embedded applications.
During that time he served as a member of Honeywell’s Program Technical
Advisory Board to MCC and was an Adjunct Faculty and taught in the Department
of Electrical Engineering at the
Dr. Yalamanchili is a Senior Member of the IEEE and contributes professionally with regular service on editorial boards and conference & workshop program committees.
Research
My current research interests are driven by two sets of challenges. The
first set of challenges is that of the design and analysis on-chip
architectures in the presence of process, voltage, and temperature (PVT)
variations. As the computing industry enters
the deep submicron region of semiconductor design it is faced with the
challenges of inter-die and intra-die process variation that will cause
defect-free yield to drop sharply. Our approach is to develop technique for
continuous, on-line tuning to adapt to static (initially) and time-varying
variations. We focus on the cache hierarchy developing techniques for scaling
cache designs and on the on-chip interconnects developing techniques for
on-line tuning of links and local, on-line configuration of link and switch
resources for fault and energy management.
The emergence of heterogeneous
systems comprised of homogeneous general purpose cores intermingled with
customized heterogeneous cores and using diverse memory and cache hierarchies
has been well documented. Such will be the case both on chip as well as in rack
scale and multi-rack scale systems in the enterprise and supercomputing arena. The second set of
challenges is in architecting heterogeneous architectures, specifically
focusing on issues of execution models, memory systems, and supporting run-time
abstractions and their associated implementations and architectural support. We
currently are working with accelerators based on FPGAs,
the Cell BE, and NVIDIA CUDA.
I would like to gratefully acknowledge the generous support of past and current research efforts by the National Science Foundation, Defense Advanced Projects Agency, Department of Energy, National Aeronautics and Space Administration, Sandia National Laboratories, Office of Naval Research, Xilinx, and Intel Corporation.
Academic
My teaching interests have been consumed in part by the introductory computer engineering course at Georgia Tech: ECE 2030. In addition, these days I typically teach the undergraduate and graduate courses in computer architecture and regularly contribute to periodic curricular efforts.
ECE
2030: Introduction to Computer Engineering (Spring 2008)
ECE
4100/6100: Advanced Computer Architecture (Fall 2006)
ECE 4170: Introduction to HDLs with Application to Digital Design (Spring 2007)
ECE 3055: Computer Architecture and Operating Systems (Summer 2008)
In recent years I have devoted time to the development of the following textbooks.
Interconnection Networks,
J. Duato, S. Yalamanchili, L. Ni, Morgan Kaufman,
2003.
VHDL
Starters Guide, 2nd Edition, Prentice Hall, 2004
VHDL
Problems with this page? Please contact: Sudhakar Yalamanchili at sudha@ece.gatech.edu