Sudhakar Yalamanchili
Professor
The School of
Electrical and Computer Engineering
Georgia Institute of Technology
Mailing Address:
Phone: (404) 894-2940
Fax: (404) 385 1746
Office: KACB 2316
Email: sudha@ece.gatech.edu
Scheduled Weekly Meetings: Fall 2009
Research: Computer Architecture and Systems Laboratory
Teaching (Fall 2009): ECE 2030: Introduction to Computer Engineering
Sudhakar Yalamanchili received the B.E degree in Electronics from Bangalore
University, India in 1978, and the MS. and Ph.D degrees in Electrical and Computer
Engineering from the University of Texas at Austin in 1980 and 1984
respectively.
He is currently a Joseph M. Pettit Professor of Computer Engineering in the School of
Electrical and Computer Engineering at the Georgia Institute of Technology in Atlanta
GA. Prior to joining Georgia Tech in 1989 he was Senior and then Principal
Research Scientist at the Honeywell Systems and Research Center in Minneapolis
from 1984 to 1989. At Honeywell he was the Principal Investigator for projects
in the design and analysis of multiprocessor architectures for embedded
applications. During that time he served as a member of Honeywell’s Program
Technical Advisory Board to MCC and was an Adjunct Faculty and taught in the
Department of Electrical Engineering at the
Dr. Yalamanchili is a Senior Member of the IEEE and contributes professionally with regular service on editorial boards and conference & workshop program committees. Most recent service includes Program Committees for the 2009 International Symposium on High Performance Computer Architecture, 2010 International Symposium on Networks on Chip, and the 2009 International Conference on High Performance Computing.
Research
My current research interests are driven by two main foci. The first is the need for an infrastructure for
modeling and evaluation of many core architectures and systems. The Manifold project seeks to develop an
open source infrastructure for workload-driven parallel simulation of many core
architectures. The project will also provide software support for integrating
existing point tools and models, for example through i) simulation kernels to support via standardized
APIs necessary event, synchronization and time management services and ii)
productivity tools for model management, deployment, visualization, etc. An
important contributing factor to the design is the need to make available an
infrastructure for classroom use in both undergraduate and graduate education.
In my group, Manifold usage is
being driven by exploration of two research themes – i) architectural and
control-theoretic techniques for managing power and thermal behaviors, and ii)
integration of interconnection networks and memory systems.
The second area of focus is on
the emergence of heterogeneous systems comprised of homogeneous general purpose
cores intermingled with customized heterogeneous cores and using diverse memory
and cache hierarchies. Such architectures will be prevalent in both on chip as
well as in rack scale and multi-rack scale systems in the enterprise and
supercomputing arena. Our focus is on improving the productivity of software development for
such architectures. Our research is coalesced around two system efforts. The
first is the Harmony run-time system which implements an execution
model for the portable execution of applications and explores techniques such
as i) speculative kernel execution, ii) memory renaming optimization to improve
kernel concurrency, and iii) on-line construction of performance models. The
second is the Ocelot infrastructure that includes architecture
emulation and compilation functions. Ocelot can be coupled
with Harmony to explore techniques for efficient and effective
execution of applications on high core count heterogeneous systems.
We gratefully acknowledge the generous support of our current research efforts by the National Science Foundation, Sandia National Laboratories, LogicBlox Corporation, HP Labs, Intel Corporation, IBM Corporation, IMPACT Technologies LLC, and NVIDIA Corporation.
Academic
My teaching interests have been consumed in part by the introductory computer engineering course at Georgia Tech: ECE 2030. In addition, these days I typically teach the undergraduate and graduate courses in computer architecture and regularly contribute to periodic curricular efforts.
ECE
2030: Introduction to Computer Engineering
ECE
4100/6100: Advanced Computer Architecture (Spring 2009)
ECE 4170: Introduction to HDLs with Application to Digital Design (Spring 2007)
ECE 3055: Computer Architecture and Operating Systems (Summer 2008)
In recent years I have devoted time to the development of the following textbooks.
Interconnection Networks,
J. Duato, S. Yalamanchili, L. Ni, Morgan Kaufman, 2003.
VHDL
Starters Guide, 2nd Edition, Prentice Hall, 2004.
VHDL: From Simulation to Synthesis, Prentice Hall, 2000 (reprinted in
Japanese, 2002)
Problems with this page? Please contact: Sudhakar Yalamanchili at sudha@ece.gatech.edu