CmpE 4170: Introduction to HDL with Applications to Digital System Design

2006 Spring Semester

Instructor	Prof. Sudhakar Yalamanchili
Office/Lab	TSRB 438
Phone	404-894-2940
E-Mail	sudha@ece.gatech.edu
Office Hours	MW 2:05-4:25 in CoC 358
TAs and Office Hours:	Tushar Kumar 2:30-4:00 pm , TTH

Prerequisite: ECE 2031 Course Objective: Introduction to hardware description languages and associated methodologies for digital system design. In depth coverage includes applications to the simulation and synthesis of digital systems. Detailed coverage of VHDL with introduction to competing hardware description languages and approaches. The course has a significant project component to re-enforce language concepts in the context of modern systems-on-chip. Recommended Text:  VHDL: From Simulation to Synthesis, S. Yalamanchili, Prentice Hall (pubs.). Alternative sources of information, class notes, and supplemental readings will be assigned.
Exams:	See schedule below
Attendance: Students are responsible for all material covered in class, including changes in exam schedules announced in class. Make-up exams will be considered only if the student informs the instructor of the absence prior to the exam date, or, when prior information was not possible, immediately following the exam. Make-up exams are not guaranteed to be the same as the exam given in class. Academic Honesty: Although students are encouraged strongly to work together to learn the course material, all students are expected to complete quizzes and exams individually, following all instructions stated in conjunction with the exam. All conduct in this course will be governed by the Georgia Tech honor code. Additionally, it is expected that students will respect their peers and the instructor such that no one takes unfair advantage of anyone else associated with the course. Any suspected cases of academic dishonesty will be reported to the Dean of Students for further action.

Schedule of Lectures

(Note this is a plan and subject to change as the course progresses)

Class #	Date	Topic	Assignments	Schedule
1	January 9^th	Introduction and Course Overview
2	January 11^th	Modeling Digital Systems: Simulation vs. Synthesis
3	January 16^th	School Holiday
4	January 18^th	VHDL Basic Language Concepts: Simulation, and Delay Models	HW #1
5	January 23^rd	VHDL Basic Language Concepts: Synthesis
6	January 25^th	VHDL Basic Language Concepts: Synthesis	Project Proposal OpenRISC SoC Structure
7	January 30^th	Describing Complex Behavior: Simulation		HW #1 Due
8	February 1^st	Describing Complex Behavior: Simulation	HW #2 ISA Definition Datapath Definition	HW # 2 Distributed
9	February 6^th	Basic Input Output: File I/O and the TEXTIO Package		Project Proposals Due
10	February 8^th	Describing Structure
11	February 13^th	Describing Structure
12	February 15^th	Essentials of Functions and Procedures		· HW# 2 Due/ HW #3 Distributed · Feedback on Project Proposals · Project Requirements Format Distributed
13	February 20^th	Essentials of Functions and Procedures	HW #3 Assembler
14	February 22^nd	Midterm
15	February 27^th	Programming Mechanics	HW #4	· HW #3 Due · HW #4 distributed
16	March 1^st	Operators, Identifiers, & Types		Project Functional Design Format provided
17	March 6^th	Describing Complex Behavior: Synthesis
18	March 8^th	Describing Complex Behavior: Synthesis
19	March 13^th	The OpenRISC SoC Infrastructure
20	March 15^th	Tutorial Session in the Laboratory		HW #4 due March 17^th Functional Design Document Distributed
21	March 20^th	Spring Break
22	March 22^nd	Spring Break
23	March 27^th	Introduction to Verilog	You might find this document useful.
24	March 29^th	Introduction to Verilog		Functional Design Due March 31^st
25	April 3^rd	Standards: 1076.3, 1076.4, 1076.6 and Introduction to Behavioral Synthesis		Note: These are for class/personal use only and are not to be distributed! They were provided from publicly available websites.
26	April 5^th	Behavioral Synthesis: Optimizations		Note: These are for class/personal use only and are not to be distributed! They were provided from publicly available websites.
27	April 10^th	Open Core Protocol		Project Calendar
28	April 12^th	Open Core Protocol
29	April 17^th	Class Presentations		Status Update: Interim Design Reviews
30	April 19^th	Generic Reconfigurable Architecture Compilation Environment: GRACE Tutorial
31	April 24^th	Generic Reconfigurable Architecture Compilation Environment: GRACE Tutorial
32	April 26^th	Summary and Wrap up		Final Project Reports Due
33	May 3^rd	Final Examination (2:50 – 5:40)

Questions and comments to Sudhakar Yalamanchili
last revised on April 2006