Prerequisite: ECE 6100: Advanced Computer Architecture
Course
Objective: Cover the core
architectural concepts of modern multiprocessor interconnection networks and the
associated formal methods for the design of deadlock-free and livelock free routing protocols. Coverage includes recent
standards, and the latest papers on router microarchitecture, network
optimization, performance optimization, and technology dependence
Texts:
“Interconnection
Networks: An Engineering Approach”, J. Duato, S.
Yalamanchili and L. Ni, Morgan Kaufmann (pubs.), 2003
Journal and
conference papers
Course
Syllabus: Syllabus
Instructor: Sudhakar
Yalamanchili
Contact Information:
KACB 2316, Email: sudha@ece.gatech.edu,
Tel: 404-894-2940
Fall 2010 Office Hours: TTH: 1:30 – 3:00, M: 9:30 – 11 TTH, email
most anytime
Section TA:
none
Exam
Schedule:
Exam I (20%): October 7th, 2010. Start:
9AM, End: 6pm (No late submissions will be accepted). Details to be provided.
Assignment Schedule:
1.
Assignment 1
Simulator Overview (ppt)
2. Assignment 2
Projects:
Projects are to be executed individually. If you wish to propose a group
project, the level of effort must be commensurate with the number of people.
Please discuss this early in the semester with me. A more detailed timeline
will be forthcoming. Some suggestions for projects can be found here
Logistics
Attendance:
Students are
responsible for all material covered in class, including changes in exam
schedules announced in class. Make-up exams will be considered only if the student
informs the instructor of the absence prior to the exam date, or, when prior
information was not possible, immediately following the exam. Make-up
exams are not guaranteed to be the same as the exam given in class.
Academic
Honesty: Although students
are encouraged strongly to work together to learn the course material, all
students are expected to complete assignments and exams individually, following
all instructions stated in conjunction with the exam. All conduct in this course will be governed by the Georgia Tech honor
code. Additionally, it is expected that students will respect their peers
and the instructor such that no one takes unfair advantage of anyone else
associated with the course. Any suspected cases of academic dishonesty will be
reported to the Dean of Students for further action.
Schedule of Lectures
Note that IEEE/ACM papers
are electronically available through the library
and are governed by
copyrights that you are responsible for honoring.
|
Module |
Last Update |
Lecture |
|
Notes/Additional
References |
|
1 |
|
1.1-1.4 |
|
|
|
2 |
|
2.1, 2.2 |
||
|
3 |
|
2.3-2.8 |
||
|
4 |
|
1.4-1.9 |
Overview,
Generalized
Hypercubes, Switch
Speedup Express Cubes,
Flattened
Butterfly, FB-On-Chip,
Fat Tree
(Classic Paper), Fat Tree
Structure, Dragonfly |
|
|
5 |
|
Deadlock
and Livelock – I (ppt,
pdf)
, Deadlock and Livelock –II (ppt,
pdf) |
Chapter 3 |
|
|
6 |
|
|
References to
papers are embedded in the lecture notes |
|
|
7 |
|
|
References to
papers are embedded in the lecture notes |
|
|
8 |
|
|
References to
papers are embedded in the lecture notes |
|
|
9 |
|
Integration
with Memory Systems |
|
|
|
10 |
|
Case
Studies |
|
|