Building Blocks

Module 6

Reading Assignment s Mano & Kime (4^th ed.) Sections 3-7, 3-8, 3-9: pp. 121-139 Sect. 6-8: pp. 319-329 Supplement for Xilinx FPGAs	Schedule of Lectures	Sample Problems 2,3,7
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Decoders

• May be viewed as selecting one of  2^N outputs thereby decoding the binary input values
• Decoder truth table and icon
• example block
• Outputs correspond to minterms
• Gate level implementation
• Application to the tri-state bus
• What if no sources are transmitting?
• Want ALL t-gate select lines = 0 (need to distinguish from input =0)
• Add an enable line to the decoder
• if enable = 0, ALL outputs = 0
• otherwise, decoder works normally
• logic implementation
• Boolean function implementation with a decoder
• Outputs correspond to minterms
• example
• Hierarchical construction of decoders

Encoders

• Input is a group of parallel bits where a single bit is a 1 and all others are 0's 
• Output is a binary code representing which input bit = 1
• Truth table
• What happens when all inputs are inactive? 
• Output valid or output enable signal
• Output is valid only when the output enable is asserted
• Example block
• Application

Priority Encoders

• What happens if more than one input is active? 
• Truth table? 

A3 A2 A1 A0	B1 B0
0  0  0  0    0  0  0  1    0  0  1  0    0  0  1  1    0  1  0  0    0  1  0  1    0  1  1  0    0  1  1  1    1  0  0  0    1  0  0  1    1  0  1  0    1  0  1  1    1  1  0  0    1  1  0  1    1  1  1  0    1  1  1  1	?  ?    0  0   0  1    ?  ?    1  0   ?  ?    ?  ?    ?  ?    1  1   ?  ?    ?  ?    ?  ?    ?  ?    ?  ?    ?  ?    ?  ?

• Establish a priority ordering of inputs and encode highest priority input
• Truth table for priority encoder with valid output 

A3 A2 A1 A0	B1 B0 V
0  0  0  0    0  0  0  1    0  0  1  x    0  1  x  x    1  x  x  x	x  x  0    0  0  1    0  1  1    1  0  1    1  1  1

• Can be designed as a priority resolution function followed by an encoder
• Use Kmaps to simplify

o example

Multiplexors/Demultiplexors

• Multiplexor
• How can we control access to shared datapaths, e.g. several inputs to one output?
• Truth table
• Value on the select lines determines input/output connection
• example block
• SOP representation and Gate Level Implementation
• Implementation using transmission gates
• example
• w-bit wide paths
• Hierarchical construction
• Boolean function implementation with a multiplexor
• Truth table entries correspond to input values
• Select lines correspond to minterms

1. example

• Reduction and implementation with a  smaller multiplexor

1. example

• Demultiplexors
• Fan-in and fan-out considerations: what do we do about them?
• Minimize the load placed on external circuits 
• Use inverting or non-inverting buffers:  buffered designs
• example
• w-bit paths
• Example  of a shared datapath: 4 sources and 8 destinations over a single bit channel
• alternative implementation using a tri-state bus

Programmable Logic Devices

• Fixed underlying set of components such as gates and switches with programmable interconnect
• Permanent or re-programmable switch points: fuses vs. transistors
• Read only memory: a version using gates and building blocks
• Using ROMs to implement functions, e.g., N²
• Example
• PLAs can be programmed to realized any Boolean function in their canonical form
• Implementation of AND/OR planes 
• Example
• PALs: AND plane is programmable but the OR plane is not
• Example
• Field Programmable Gate Arrays
• Implementing combinational logic using look-up tables

Parity Generators

· Generate an extra bit to encode even/odd number of bits with value 1

· Generate parity at the receiver and compare

o Can detect certain classes of errors

Building Blocks: Summary

• Implement combinational functions using any one of
• Decoder + OR gate
• Multiplexor,  invertor, 1 and 0 signals
• PALs and PLAs
• FPGAs