Counters

Module 10

Reading Assignment Sec. 7-6: pp 357-366	Schedule of Lectures	Sample Problems
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Behavior

• State diagrams concisely capture the behavior of counters 
• Implementations of counters are with registers whose sequence of values  correspond to the count
• General register design principles apply: 
• Serial/parallel load, enable, initialize, clear
• Applications
• counting cars in a parking lot: block diagram
• clock generation: block diagram

Synchronous Counters

• Introduction of the toggle cell
• With toggle enable and asynchronous active low CLR
• Simple 1-bit counter

• How can we cascade these cells to produce a multi-bit counter?
• 2-bit and 4-bit counter
• All CLR signals and clock signals are connected together
• Timing diagram

• Synchronous operation implies clock is applied to all inputs concurrently
• What does the combinational logic look like?
• Force flip flops into values that depend on the current set of flip flop values

General Design Considerations

• What if we wish to have the counter cycle through a different sequence of values?
• For example 0-1-2-3-4-5-0?
• We need to reinitialize the counter to 000 after it reaches state 5
• state diagram
• implementation

• We can re-intialize the counter to any initial state by using both Set and Reset inputs of each flip flop
• Parallel/serial load to initialize a counter to any initial value

General Design Methodology for Synchronous Counters

• We know the number of bits required for the counter and we know how to design combinational logic! 
• General behavior
• upcounter: state diagram (4 bit)
• downcounter: state diagram (3 bit)
• up/down Counter: state diagram (3 bit) 
• We can design this counter from first principles using logic design techniques
• upcounter Design: state transition table and KMaps+equations .
•  Implementation
• Implementation from the state transition table
• Bit slice implementation
• Notice that the equation for each more significant bit can use the terms generated for the preceding bits
• This allows us to build a "counter bit cell" that is identical for every position in the word
• Now we can add parallel load capability to initialize the counter to any value.
• This produces a counter similar to the one we started with using toggle cells!
• Important!: This is a general methodology for designing any counter
• Can we generalize this design strategy beyond counters? Yes --> state machines!

Other Types of Counters: Example - Ring Counter

• Behavior and state diagram
• Initialize shift register with the LSB set
• Each clock cycle the bit is shifted up with the MSB connected to the LSB
• The count is given by the position of the 1-bit
• This is a modulo-m counter with m bits
• Implementation