CmpE 2030: Introduction to Computer Engineering

Index

A

active low

adder

addressing

addressing mode

address space, memory

algebraic methods

arithmetic

ASCII

B

barrel shifter

Boolean algebra

Boolean identities

branch instructions

C

clocks

control flow

controller

counters, synchronous

D

decoder

D-latch

DRAM

E

encoder

F

feedback

floating point

G

gate design

H

hierarchy

I

if-then-else

implicants

instruction format

instruction set architecture (ISA)

L

logical unit

loops

K

K-maps

Karnaugh maps

M

maxterms

Mealy machine

memory chip

memory system

microcode

minterms

mixed logic

Moore machine

Moore’s Law

multiplexor

N

negative logic

next state function

notation

O

optimization (K-maps)

output function

P

parameter passing

pointer

positive logic

procedure call

product of sums (POS)

propagation delay

prime implicants

priority encoder

priority resolution

program counter

programmable logic device (PLD)

programmable logic array (PAL)

programmable array logic (PLA)

R

register

register cell

register file

representation

ring counter

S

sequential logic

shift register

shift unit

SRAM

SR-latch

stack

standard forms

state machines

state transition table

subtractor

sum of products (SOP)

switches

switching networks

switching networks, animations

switch implementation NAND

switch implementation NOR

switch implementation INVERT

switch implementation COMPLEX

T

transistor switch models

tri-state drivers

U

universal gates

W

while loop