Datapaths

Module 13

Reading Assignment	Schedule of Lectures	Sample Problems Datapath Elements: 2,3 Single Cycle Datapath: 1, 4,6
Previous Lecture	Next Lecture	The SPIM Simulator Supplemental Material 1 Supplemental Material 2 Microcode Template

Datapath Elements

Adder/Subtractor

• 32 bit integer unit
• Refer to the design covered in the arithmetic module

Register File

• Review single bit register design
• Organize a group of multi-bit registers into a file
• Each register is identified by a unique register name or address: a numeric value
• Register file operations
• Load any register in the file: register file  store or write operation
• Read any register in the file: register file  read operation
• Single port register file: single input, single output
• Register file input
• Demultiplex register file data input to all register inputs
• Decode the input address to produce the write enable for the desired register
• Register file output
• All registers drive the output bus
• Decoder is used to produce the read enable signals to select the correct register that will drive the bus!

• Extension to a dual port register file: two read ports and one write port

Logical Unit

• Implementation of any truth table of two variables using a 4:1 multiplexor (review)
• All truth tables for two variables (review)
• Extension to logical operations on 32 bit quantities
• Parallel operation of 32 single bit implementations à the bit slice model
• Operation
• Specify the truth table on two variables: this requires four bits
• Output Enable
• Can perform any bit-wise logical operation on two 32 bit operands
• Examples:
• AND : lf = 1000
• OR : lf = 1110
• XOR : lf = 0110
• Applications of logical operations
• Masking of bit fields
• Examples of logical operations on 32 bit words
• Examples: image processing, cryptography (RC6)

Shift Unit: A Barrel Shifter

• Logical, shifts, arithmetic shifts, and circular shifts (rotate)

• Examples of multiplication and division using shifts for unsigned and two’s complement numbers
• Converting a 16 bit number to a 32-bit number and sign extension

• Bi-directional 1-shifter using 4:1 multiplexors

·

• When S =1 the value of d determines whether it is a left or right shift
• The value of V may 0, 1 or the value of the least significant bit (rotate right)
• Similar design for the multiplexor in the least significant bit position
• Bi-directional p-shifter using 4:1 multiplexors
• p= 2^k
• Boundary conditions
• Addition is performed modulo the number of bits in the word

• Any shift operation can be composed of power-of-two shift operations
• Barrel shifter implementation using logarithmic stages of 2^k-shifters

• Remember any number can be represented in binary!
• For bit position i  the value shifted into the bit position may one of four values (k = shift amount)
• a_i-k , a_i+k , 0, or 1 (at the ends)
• For rotate operations the shift input at the end may be a_n-1 (rotate left) or a₀ (rotate right)

• Shift Registers: Arithmetic vs. logical shifts

• These techniques can be used to implement a generic shift unit

A Single Cycle Datapath

• Provide an interconnection to support the flow of data values from the registers à functional units à registers (results)
• Provide control circuitry and we have a datapath!

Architecture of a Datapath

• Register file + functional units: adder/subtractor, logical unit, barrel shifter
• Shared buses connect the inputs and outputs of the functional units and the register file
• Buses reduce wiring complexity
• The source unit providing data on a bus is determined by the functional unit enable signals
• Use of the buses must be scheduled to permit only one source at a time
• Use of immediate operands and the immediate register
• Multiplex register file source and immediate operand onto the X bus
• Arithmetic/Logic datapath

Operation

• A single arithmetic or logical operation on the contents of a pair of registers can be performed by specifying the values of all control signals
• Sample sequencing and operation for adding two registers
• Control signal values are structured into a control word or microinstruction
• Associated groups of control signals can be referred to as fields
• for example, the shift unit field is comprised of all signals that control the shift unit
• Organization of control words into a fields is referred to as a format

Step

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rwe

im en

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description

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• A sequence of arithmetic/logical operations can be performed by successive application of the corresponding sequence of control words
• A sequence of microinstructions is referred to as a microprogram.
• Programs written in this form are generally referred to as microcode
• Examples
• Register transfer notation
• A convenient notation for expressing an operation
• for example, R1 = R2 + R3  : add the contents of registers R2 and R3 and place the resulting value in register R1
• A single arithmetic or logical operation can be expressed as a register transfer operation
• General computations (expressions) can be translated into a sequence of register transfer operations which in turn can be implemented as a Sequence of   microinstructions
• For example R1 = 2(R2 + R4) - R6 can be implemented as the following three steps

R2 = R2 + R4
R2 = left shift R2 by 1 bit (corresponds to a multiplication by 2)
R1 = R2 - R6

• Multiplication and division can be implemented by left and right shifts respectively
• For example R1 = 3(R2) can be implemented by the sequence

R1 = left shift R2 by 1 (multiplication by 2)
R1 = R1 + R2

• Example microprograms for expression evaluation

Need for Memory

• Register file provides limited storage
• What if we need more storage? à memory!
• Store data in memory and move to register file for operation
• Move back to memory after operation
• Register file serves as temporary storage
• How do we specify which memory location is to provide the data? à memory address!
• Memory interface
• Address and data (for store)  on X and Y buses respectively
• Load data on the Z bus
• Additional control signals for memory: r/-w, msel, ld en and st en

• What does the microinstruction look like now?

step

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• Microinstruction for memory read
• Referred to as a load word operation: R1 = M[R2]

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R1=M[R2]

• Microinstruction for memory write
• Referred to as a store word operation: M[R2] = R1

step

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M[R2]=R1

• All quantities are 32 bits

Addressing Modes

• There are alternative ways in which to think about addresses in memory
• Register indirect mode (R1 = M[R2])
• Indexed addressing modes (R1 = M[R2 + 4*i] where i = offset in words/elements)
• use of the immediate register for the offset
• any register may be used for the base
• addressing modes may be supported in hardware or software
• Addresses are first constructed in a register prior to a load or store operation
• General memory access issues
• load/store bytes
• load/store halfwords
• Revisit the memory alignment issue
• Big endian vs. little endian is a storage issue; it does not change the value!

Writing Microcode

· Structured Approach to solving problems

o Algorithm pseudo code

o Register/memory allocation (variables and data structures)

o Translate to RTL notation

o Translate each RTL statement to microcode

Examples

• Commercial processor examples
• The programming model is at the level of microcode
• Expression evaluation: arithmetic
• Expression evaluation: Boolean
• Memory operations: load/store
• Computations with data in memory: pixel averaging

Questions and comments to Sudhakar Yalamanchili