Memory

Module 12

Reading Assignment	Schedule of Lectures	Sample Problems 1,2,5,6
Previous Lecture	Next Lecture	The SPIM Simulator Memory Timing Supplemental Material

Static Random Access Memory (SRAM)

• Review register protocol
• Memory cell implementation (6T: six transistor)
• Behavior
• Bistable device
• Memory cell protocol versus register cell protocol
• Read/Write timing
• Some commercial SRAM numbers
• Cache memories in modern processors

Dynamic Random Access Memory (DRAM)

• Memory cell implementation (1T: one transistor)
• Behavior
• Destructive readout
• Charge leakage and refresh hence dynamic
• High density
• Memory cell protocol
• Read/Write timing
• Some commercial DRAM numbers

Architecture of a Memory Chip

• Bit organization as a 2-D array of RAM cells
• Major operational components
• Row select and row decoder
• Column select and column decoder
• Chip select and write enable
• Multibit access
• Chips may share data signals or have distinct signals for input and output
• DRAM chips have additional circuitry to support refresh operations
• Part types, e.g., 16Mx1, 4Mx4, 1Mx8
• Multiple banks
• Addresses vs. contents

Types of Random Access Memories

• The chip architecture remains largely the same with timing optimizations
• Synchronous Dynamic RAM (SDRAM)
• Modes
• Page mode
• Burst mode

Building Memory Systems

• The architecture of a memory system characterized by two parameters
• Number of addresses
• The number of bits at each address
• Building with 4 Mbit chips (1M x 4)
• One million addresses by eight bits

• Two million addresses by four bits

• Four million addresses by four bits

• Two million addresses by eight bits

• General memory systems parameters
• Memory access time
• Memory bandwidth
• Large memory system examples

A Logical View of Memory

• Address space
• Memory can be viewed as linear array of physical locations
• The index into this array is an address
• A contiguous range of addresses (typically starting at 0) is an address space
• Alignment
• Byte, half word, and word addresses
• Byte and word address boundaries
• General 2ⁿ byte address boundaries

• Storage
• An address is distinguished from the contents stored at that address
• How does the preceding map back to the physical model?

• Example: value 0x76 may be stored at byte address 0x04000022
• Example: value 0x32334467 may be stored at word address 0x0400000c
• How are words stored in a byte addressed machine?
• Big endian vs. little endian
• is the most significant byte or least significant byte (i.e., "big end" or "little end") of the word stored at the word boundary
• in a byte addressed memory the word boundary is the byte whose binary address ends in 00 or hex address ends in 0, 4, 8 or c
• We must distinguish between the value and how the value is stored
• How can we specify the storage of values at specific memory locations?
• Data directives: .data, .word, .byte, .asciiz, .align, .space, .ascii
• Examples of specifications and associated memory contents
• Use the SPIM simulator that is available from the link at the top of the page
• Memory maps
• Certain address ranges may be reserved for specific purposes
• For example your program may be restricted to use some area of memory
• The operating system may reserve a certain area of memory
• Different types of data may be stored in distinct parts of memory
• Text vs. data
• User data vs. operating system data

Questions and comments to Sudhakar Yalamanchili