Outputs depend on the input and the
"state" of the system
Outputs may only change at specific points in
time
Examples
of systems that require state:
Parking lot
Process state diagram
Process IDs in an operating system
Implementation of Memory and the SR Latch
What
do we need to retain values over time?
Ability to store values
The ability to change the stored value
To
retain values indefinitely we need to understand feedback
Zero delay NAND gate with feedback: inconsistent
Non-zero delay NAND gate with feedback: oscillation
A bistable logic
circuit with two inverters and feedback: two stable states, 0 and 1
How can we change these states?
The
SR latch using NOR gates
Operation and timing
Excitation table
Problems and migration to other designs
The D-Latch
The
basic D-latch (delay latch)
Open and close the D input to let new
values in (load phase)
Open and close the feedback loop to
"capture" the value (hold phase)
Note control input in addition to the data input
Transparent
operation: D-latch
Example operation and timing
Clocks
and Periodic Waveforms
Period,
pulse width, phase, and frequency
Synchronous
vs. asynchronous operation
Introduction
of multi-phase non-overlapping clocks
Latches
and Combinational Logic
Sequential
circuits with feedback
Hold phase: no problem
Race condition
How
can we fix this problem?
Register
Cell
Consider
an organization with two latches
Two separate, non-overlapping clocks:
two-phase clocks
Master-slave
operation
De-couple input from output
Latch input on falling edge of Φ1
Enable output on rising edge of Φ2
Notion of the active edge of the clock
Definition of a clock cycle
Concurrent
Read/Write behavior
Clocking
issues
Pulse separation: speed vs. correctness
By making pulse separation arbitrarily small we
approach edge triggered designs
Issues with edge triggered designs
clocks are not perfect square waves
both transmission gates may be open leading to
indeterminate output value
input and output in master/slave design may not
be isolated
Majority of modern systems use two-phase
non-overlapping clocks
Initialization
issues
Preset and clear
Register
protocol
Clock gating vs. 2:1 input mux
Separate write enable and read enable
Register protocol and basic cell design
Concurrent read/write
Registers
Store
and manipulate multiple bits as a single unit of information
Built
as an array of register cells
Parallel
load
Bit, byte, and word widths
Synchronous operation
all flip flops use the same clock
all flip flops load a value on the clock cycle
Loading a value is initialization
Controls
Load register: register write or store
operation
Access register value: register read
operation
Serial Load
Register (Shift Register)
Connect
each cell's output to the next cell's input
At
each clock, load one bit and shift old bits down
Takes
N clock cycles to load entire word
Outputs
are always available in parallel form AND in serial form
Used as a serial to parallel converter
Include
a MUX on each input to allow "hold" mode and "shift"
mode
Combining
parallel and serial load capabilities
Add a MUX on each input to select between
"shift" mode and "parallel load" mode
Used as a parallel-to-serial and erial-to-parallel converter
Applications of
Shift Registers
Modem:
We need to use both a series-to-parallel
converter and a parallel-to-series converter to match internal (logic:parallel) and external (phone line: serial)
line widths
Using parallel communication over long distance
is bad, since you need to run 8 or 16 or