ECE 3055: Computer Architecture and Operating Systems

 

Summer 2008

 

Prerequisite: CS 2031 Digital Design Laboratory

Course Objective: Core concepts of computer architecture and operating systems. Instruction set architectures (ISA), compiler/ISA relationships, pipelined datapaths. Memory hierarchy, memory management, and protection. Processes, threads, CPU scheduling and associated techniques.

Texts:

Patterson and Hennessey, Computer Organization & Design: The Hardware/Software Interface (3rd edition), Morgan Kaufmann, 2004. ISBN 1-55860-604-1.    Silberschatz, Galvin, and Gagne, Operating System Concepts with Java (7th edition), John Wiley, 2004. ISBN-13: 978-0471694663

Course Syllabus:   Syllabus

 

 

 

Instructor: Sudhakar Yalamanchili

Contact Information: KACB 2316, Email: sudha@ece.gatech.edu, Tel: 404-894-2940

 

Summer 2007 Office Hours: MW 4:30 PM – 6 PM, TTH (by appt.)

 

Section TA: Jimmy Simmons

Office Hours: http://www.google.com/calendar/embed?src=simmons.jimmy%40gmail.com&ctz=America/New_York

Email: jimmy.simmons@gatech.edu

 

 

Exam Schedule:

 

Exam I (20%):    Monday June 9th, 2008, Exam I, Exam-I Solutions

Exam II (20%):  Monday July 21st, 2008

Final Exam (30%): Wednesday, July 30th, 2008, 2:50 PM – 5:40 PM

 

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Assignment Schedule:

 

Assignment 1, SPIM Template: Due Wednesday, May 28th, 2008 @11:59pm (no late submissions).

 

Look to TSquare for distribution and submission of assignments and associated materials

 

 

 

Attendance: Students are responsible for all material covered in class, including changes in exam schedules announced in class. Make-up exams will be considered only if the student informs the instructor of the absence prior to the exam date, or, when prior information was not possible, immediately following the exam. Make-up exams are not guaranteed to be the same as the exam given in class.

Academic Honesty: Although students are encouraged strongly to work together to learn the course material, all students are expected to complete assignments and exams individually, following all instructions stated in conjunction with the exam. All conduct in this course will be governed by the Georgia Tech honor code. Additionally, it is expected that students will respect their peers and the instructor such that no one takes unfair advantage of anyone else associated with the course. Any suspected cases of academic dishonesty will be reported to the Dean of Students for further action.

 

 

 

Schedule of Lectures

 

 

Module

Last Update

Lecture

Reading (Note Appendices are found on the CD)

Notes/Additional References

1

5/10/2008

Overview and Introduction

Ch. 1

 

2

5/10/2008

MIPS ISA Part I: ISA & Encodings

Ch. 2.1 – 2.6, 2.9

Class Resources Page

Handy Wikipedia Ref

3

5/10/2008

MIPS ISA Part II: Procedures and System Software Aspects

Ch. 2.7, 2.10, 2.15, 2.16

Ref: A.2 – A.5

Ref: A.6 (proc. calls), A.9, A.10

5

5/10/2008

ALU and Arithmetic  

App B.5 – B.7

Ch. 3.2 – 3.4

 

6

5/10/2008

Single Cycle Datapath

Ch. 5.3 - 5.4

Ref: C.2

VHDL Model Source

7

5/10/2008

Multi-Cycle Datapath

Ch. 5.5- 5.6

Ref: C.3-C.5, A.7

VHDL Model Source

8

5/10/2008

Pipelined Datapath

Ch. 6.1–6.6 (pg. 416-420), 6.8

Ref: 6.7 on the CD

VHDL Model Source

9

5/10/2008

Measuring Performance

Ch. 4.1, 4.2

Ref: Appendix 4.49, 4.34

10

5/10/2008

Cache Memory Hierarchy

Ch. 7.1 – 7.4, 7.6

 

11

5/10/2008

Virtual Memory

Ch. 8, Ch. Ch. 9.1-2, Ch. 9.4-9.6

 

12

5/10/2008

Processes & Threads

Ch. 3.1 - 3.3, Ch. 4.1 – 4.3, Ch. 4.5-4.6

 

13

5/10/2008

Synchronization

Ch. 6.1- 6.7

pthreads reference

Examples: Example 1 & Example 2

14

5/10/2008

CPU Scheduling

Ch. 5

 

 

7/30/2008

Final Exam: 2:50 PM – 5:40 PM