ECE 3056: Architecture, Concurrency, and Energy  in Computation

 

Fall 2012

 

Prerequisite: ECE 2035, ECE 2031

Course Objective:This course introduces the basic organizational principles of the major components of a processor the core, memory hierarchy, and the I/O subsystem. Students gain an understanding of the sources of performance and energy dissipation in modern processors and learn the multiple forms and levels of parallelism that have been employed to sustain performance improvements in the industry. Assignments using architecture‐level simulators enable the students to explore the operation and tradeoffs in performance and energy and reinforce the concepts learned in the class room.

Texts:

Patterson and Hennessey, Computer Organization & Design: The Hardware/Software Interface (4th edition, revised printing), Morgan Kaufmann, 2012, ISBN 978-0-12-374750-1 .    

Course Syllabus:   Syllabus

 

 

 

Instructor: Sudhakar Yalamanchili

Contact Information: KACB 2316, Email: sudha@ece.gatech.edu, Tel: 404-894-2940

 

Office Hours:

 

Section TA: Chad Kersey

Office Hours:  Th 9-12, VL 449 Cubicle B,  Recitations T: 6-7  VL C241

Email:  cdkersey@gatech.edu

 

 

Exam Schedule:

 

Exam I (20%):   Wednesday, October 3rd , 2012,  Exam Solutions

Exam II (20%):  Monday , November 19th, 2012

Final Exam (30%): December 12th, 2012, 2:50 pm 5:40 pm

 

 

Assignment Schedule:

 

Look to TSquare for distribution and submission of assignments and associated materials

 

 

 

Attendance: Students are responsible for all material covered in class, including changes in exam schedules announced in class. Make-up exams will be considered only if the student informs the instructor of the absence prior to the exam date, or, when prior information was not possible, immediately following the exam. Make-up exams will not be the same as the exam given in class.

Academic Honesty: Although students are encouraged strongly to work together to learn the course material, all students are expected to complete assignments and exams individually, following all instructions stated in conjunction with the exam. All conduct in this course will be governed by the Georgia Tech honor code. Additionally, it is expected that students will respect their peers and the instructor such that no one takes unfair advantage of anyone else associated with the course. Any suspected cases of academic dishonesty will be reported to the Dean of Students for further action.

 

 

 

Schedule of Lectures

 

 

Module

Lecture

Reading (Note Appendices are found on the CD)

Notes/Additional References

1

Overview and Introduction

Ch. 1.1-1.3, 1.5-1.7

 

2

MIPS ISA: ISA & Encodings (ppt, pdf)

Ch. 2, Appendix B

Class Resources Page


Some Encoding Examples (docs, pdf)


Handy Wikipedia Ref

3

MIPS ISA Part II: Procedures and System Software  (ppt, pdf)

Ch. 2 and Appendix B

Supplemental Notes: Alternative ISAs and Class Notes

 4 Arithmetic (ppt, pdf)
Section 3.2-3.6), Appendix C.5

5
Single Cycle Datapath (ppt, pdf)
Sections 4.1-4.4, C.7, C.8, C.11, D.2

6
Multicycle Datapath (ppt, pdf)
Sections B.7, D.3. D.4, D.5

7
Pipelined Datapath (ppt, pdf)
Sections 4.5 - 4.9

8
Peformance (ppt, pdf)
Section 1.4

9
Cache Hierarchy (ppt, pdf), Virtual Memory (ppt, pdf)
Sections 5.2, 5.3, 5.9

10
I/O (ppt, pdf)
Sections 6.2-6.9
Useful links for PCI Express, HyperTransport, Quickpath
11
Energy (ppt, pdf)


12
Parallelism (ppt, pdf)
Sections 7.1, 7.2, 7.3, 7.5, 7.6, 7.7