ECE 4100/6100: Advanced Computer Architecture

Spring 2009

 

 

Prerequisite: ECE 3055: Computer Architecture and Operating Systems

 

Catalog Description:  Comprehensive coverage of the architecture and system issues that confront the design of a high performance workstation/PC computer architectures with emphasis on quantitative evaluation. Credit is not allowed for both ECE 6100 and any of the following courses: ECE 4100, CS 4290, CS 6290.  

Textbook(s): 

Hennessey & Patterson, Computer Architecture: A Quantitative Approach (4th edition), Morgan Kaufmann, 2006. (required)

Course Syllabus: Syllabus

 

 

 

Instructor: Sudhakar Yalamanchili

Contact Information: KACB 2316, Email: sudha@ece.gatech.edu, Tel: 404-894-2940

 

Spring 2009 Office Hours: TTH 1 PM – 2 PM, MTH (by appt.)

 

Section TA: Jeremy Tolbert

Office Hours: W 3-4:30, F 10:30-12

Email: jeremy.r.tolbert@gatech.edu

 

 

Exam Schedule:

 

Exam I (20%):    Thursday February 12th, 2009

Exam II (20%):  Tuesday, April 7th, 2009

Final Exam (30%): 5/1/2009, 11:30-2:50 pm

 

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Assignment Schedule:

 

Look to TSquare for distribution and submission of assignments and associated materials

 

 

 

Attendance: Students are responsible for all material covered in class, including changes in exam schedules announced in class. Make-up exams will be considered only if the student informs the instructor of the absence prior to the exam date, or, when prior information was not possible, immediately following the exam. Make-up exams are not guaranteed to be the same as the exam given in class.

Academic Honesty: Although students are encouraged strongly to work together to learn the course material, all students are expected to complete assignments and exams individually, following all instructions stated in conjunction with the exam. All conduct in this course will be governed by the Georgia Tech honor code. Additionally, it is expected that students will respect their peers and the instructor such that no one takes unfair advantage of anyone else associated with the course. Any suspected cases of academic dishonesty will be reported to the Dean of Students for further action.

 

 

Important Information Regarding Papers:

i)                             Links are provided here as a courtesy as you have access to the same through the library and

ii)                          You are required to honor the terms of the copyright

Schedule of Lectures

 

 

Module

Last Update

Lecture

Required Reading (Note Appendices are found on the CD)

Notes/Additional References

1

1/11/2009

Overview

Introduction

Instruction Set Architecture

Pipelining Review

Section 1.1 – 1.5

Appendix A.1 – A.4

Appendix B.1 – B.8

Appendix J.1

Moores Law

ITRS Roadmap

Original Moore’s Law Paper

 

Interesting Paper Readings
Suggested Paper Readings

 

2

1/11/2009

Hardware Scheduling

Appendix A.7,A.8

Section 2.4, 2.5

Sample Problems: Dependencies

Sample Problems: HW Scheduling

 

Suggested Reading: Papers

3

1/19/2008

Branch Prediction

Appendix A.2 (A.21-A.26),

Section 2.4, 2.9

Required Reading: Papers

Sample Problems: Prediction

4

2/1/2009

Performance Evaluation

Instruction Scheduling Part I

Section 1.8, 1.9, 1.10

Section 2.2

 

5

2/1/2009

Speculation

Section 2.6, 2.9

Required Reading: Papers

Suggested Reading: Papers

Sample Problems: Speculation

6

2/1/2009

Instruction Scheduling Part II

Appendix G.3

Suggested Reading: Scheduling & Iterative Modulo Scheduling

Sample Problems: Scheduling

7

2/6/2009

Instruction Fetch

Section 2.10,

Required Reading: Papers

 

8

2/19/2009

VLIW/EPIC

Appendix G.4, G.5, G.6

Required Reading: Paper

Suggested Reading: Itanium Microarchitecture and White Paper

9

2/19/2009

Multithreading

Sections 3.2, 3.3, 3.5

Required Reading: Hyperthreading

Suggested Reading: Power 5

10

2/23/2009

Caches

Sections 5.1, 5.2

Required Reading: Moore’s Law, Victim Caches, and Non-Blocking Cache

Suggested Reading: The Memory Wall, Memory Wall Revisited, and Cache Memories

Sample Problems: Memory

 

11

3/5/2009

Memory Systems

Virtual Memory

Section 5.3

Section 5.4

Suggested Reading: A DRAM Introduction and a DRAM Tutorial from UMD

12

 

Coherency (.ppt) and Consistency

Sections 4.1, 4.2, 4.4, and 4.6

Suggested Reading: Article on Memory Consistency

A few sample problems for this module

13

 

Storage Systems

Sections 6.1 and 6.2

 

14

 

Interconnection Networks (ppt, pdf)

Appendix E (relevant material)

 

15

 

Introduction to Multicore Architectures

 

 

Final Examination

5/1/2009

11:30 – 2:50