These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech and is for preliminary review purposes only. ANY REPRODUCTION OF THIS MATERIAL FOR DISTRIBUTION IS STICTLY PROHIBITED. THIS MATERIAL IS COPYRIGHT OF PRENTICE HALL PUBLISHING COMPANY, AND CANNOT BE DISTRIBUTED WITHOUT THEIR PERMISSION.

VHDL: From Simulation to Synthesis

Sudhakar Yalamanchili
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta GA
sudha@ece.gatech.edu

This text focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises and tutorials are provided for the use of the new integrated design environments from Xilinx which is available with the text. The text is targeted for use in sophomore and junior level courses in digital logic and computer architecture.

Text Materials
VHDL Resources

Text Materials

The following materials are provided for use with the text. For each chapter below you will find a brief description, a draft of the text (PDF), figures, and vugraphs for that chapter (PDF). A zip file of all of the vugraphs for the text can be conveniently downloaded here (TBD).

Chapter 1: Introduction [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
Individual VHDL language constructs can be related to digital system concepts that we are already familiar with. This chapter list fundamental physical and behavioral attributes of digital systems. Language constructs to describe each attribute will be introduced in subsequent chapters.
Simulation and synthesis are two complementary design activities: the former is descriptive while the latter is prescriptive. Understanding key attributes of each activity is necessary to understand how hardware description languages such as VHDL can be applied in the course of each activity.
Basic language constructs are introduced by associating each with a physical or behavioral attribute of digital systems. Existing knowledge of digital systems is naturally transformed into executable VHDL descriptions.
When viewed as prescription for deriving or synthesizing digital hardware, these same language constructs from Chapter 4 now acquire additional semantics.
In describing very large systems we often wish to abstract or hide the details of digital logic implementation while preserving the external behavior. Such a modeling approach can be achieved in VHDL with higher level language constructs structured in processes.
How is hardware inferred from high level descriptions described in Chapter 6, as opposed to inference from the constructs introduced in Chapter 4? Basic inference rules employed by modern VHDL synthesis compilers are reviewed to enable users to develop a consistent set of expectations with regard to how hardware is generated from high level VHDL language constructs.
The use of hierarchy and abstraction is necessary to handle large designs and consequently requires the introduction of new language constructs. A hierarchy of netlists is a standard representation in traditional digital design tools and VHDL provides language constructs for a textual description of such a hierarchy.
Abstraction is enabled in VHDL via standard programming language concepts such as procedures, functions, packages and libraries to enable design re-use, sharing, and maintainance.
Binary and text file input/output mechanisms are used to enable the integration of the results of test generation tools and the VHDL models under test. Basic error checking and testbench generation techniques are also covered.
This chapter provides an intuition about the practical aspects of VHDL environments: the terminology and mechanics of organizing, building, simulating, and synthesizing VHDL models.
A quick reference guide to the basic language syntax.
References to some excellent texts that cover more advanced features of the language.
This is a summary of the material in the text that relates to basic inference rules and the effect on the resulting synthesized hardware.
The differences between the 1987 and 1993 standards are described here.
Tutorial for Active VHDL, version 3.6, from Aldec, Inc.
Tutorial for the Xilinx Fooundation Express, version 2.1i, that is bundled with this text.
Tutorial for Synopsys FPGA Express, version 3.1, from Synopsys, Inc.
An introduction to some common packages used in VHDL models.
A program template illustrating the syntactical relationships between various VHDL constructs. A handy reference early in process of learning VHDL.

VHDL: From Simulation to Synthesis

Text Materials

VHDL Resources

Architecture