These materials are made available for  ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech and is for preliminary review purposes only.   ANY REPRODUCTION OF THIS MATERIAL FOR DISTRIBUTION IS STICTLY PROHIBITED.  THIS MATERIAL IS COPYRIGHT OF PRENTICE HALL PUBLISHING COMPANY, AND CANNOT BE DISTRIBUTED WITHOUT THEIR PERMISSION.


VHDL: From Simulation to Synthesis

Sudhakar Yalamanchili
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta GA
sudha@ece.gatech.edu

This text focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises and tutorials are provided for the use of the new integrated design environments from Xilinx which is available with the text. The text is targeted for use in sophomore and junior level courses in digital logic and computer architecture.

Text Materials
VHDL Resources


Text Materials

The following materials are provided for use with the text.  For each chapter below you will find a brief description, a draft of the text (PDF), figures, and vugraphs for that chapter (PDF). A zip file of all of the vugraphs for the text can be conveniently downloaded here (TBD).
Chapter 1: Introduction [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]

This chapter provides a very brief introduction to the place hardware description languages employ in a typical digital system design flow. Describes the genealogy of VHDL.

Chapter 2 : Modeling Digital Systems [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]

Individual VHDL language constructs can be related to digital system concepts that we are already familiar with. This chapter list fundamental physical and behavioral  attributes of  digital systems. Language constructs to describe each attribute will be introduced in subsequent chapters.


Chapter 3: Simulation vs. Synthesis [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
Simulation and synthesis are two complementary design activities: the former is descriptive while the latter is prescriptive. Understanding key attributes of each activity is necessary to understand how hardware description languages such as VHDL can be applied in the course of each activity.


Chapter 4: Basic Language Concepts: Simulation [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
Basic language constructs are introduced by associating each with a physical or behavioral attribute of digital systems. Existing knowledge of digital systems is naturally transformed into executable VHDL descriptions.


Chapter 5: Basic Language Concepts: Synthesis [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
When viewed as prescription for deriving or synthesizing digital hardware, these same language constructs from Chapter 4 now acquire additional semantics.


Chapter 6: Modeling Behavior: Simulation [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
In describing very large systems we often wish to abstract or hide the details of digital logic implementation while preserving the external behavior. Such a modeling approach can be achieved in VHDL with higher level language constructs structured in processes.


Chapter 7: Modeling Behavior: Synthesis [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
How is hardware inferred from high level descriptions described in Chapter 6, as opposed to inference from the constructs introduced in Chapter 4? Basic inference rules employed by modern VHDL synthesis compilers are reviewed to enable users to develop a consistent set of expectations with regard to how hardware is generated from high level VHDL language constructs.


Chapter 8: Modeling Structure [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
The use of hierarchy and abstraction is necessary to handle large designs and consequently requires the introduction of  new language constructs. A hierarchy of netlists is a standard representation in traditional digital design  tools and VHDL provides language constructs for a textual description of such a hierarchy.


Chapter 9: Subprograms, Packages, and Libraries [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
Abstraction is enabled in VHDL via standard programming language concepts such as procedures, functions, packages and libraries to enable design re-use, sharing, and maintainance.


Chapter 10: Basic Input/Output [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
Binary and text file input/output mechanisms are used to enable the integration of the results of test generation tools and the VHDL models under test. Basic error checking and testbench generation techniques are also covered.


Chapter 11:  Programming Mechanics [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
This chapter provides an intuition about the practical aspects of VHDL environments: the terminology and mechanics of organizing, building, simulating, and synthesizing VHDL models.


Chapter 12: Identifiers, Data Types, and Operators [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
A quick reference guide to the basic language syntax.


References [text]
References to some excellent texts that cover more advanced features of the language.


Appendix A: Synthesis Hints [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
This is a summary of the material in the text that relates to basic inference rules and the effect on the resulting synthesized hardware.


Appendix B: VHDL 1987 vs. VHDL 1993 [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
The differences between the 1987 and 1993 standards are described here.


Appendix C: Active VHDL Tutorial [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
Tutorial for Active VHDL, version 3.6, from Aldec, Inc.


Appendix D: Xilinx Foundation Express Tutorial [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
Tutorial for the Xilinx Fooundation Express, version 2.1i, that is bundled with this text.


Appendix E: Synopsys FPGA Express Tutorial [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
Tutorial for Synopsys FPGA Express, version 3.1, from Synopsys, Inc.


Appendix F: Standard VHDL Packages [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
An introduction to some common packages used in VHDL models.


Appendix G: A Starting Program Template [ figures(powerpoint), vugraphs(pdf), vugraphs(powerpoint)]
A program template illustrating the syntactical relationships between various VHDL constructs. A handy reference early in process of learning VHDL.

VHDL Resources

Links to other helpful on-line resources. This is certainly not intended to be a comprehensive list but rather a set of resources that would complement these existing resources at the level of abstraction targeted by this text,  namely, at the sophomore and junior level digital logic and computer architecture courses.
 

Architecture

Several architecture models are available for some commonly used datapaths. The following are ZIP files containing the VHDL models and associated documentation. I have also included the simulators that these models have been tested. The models are consistent with the VHDL 1086-1987 standard and I will be working to update them to the VHDL 1076-1993 standard. I expect the following models to change a bit between January 2000 and April 2000 as I upgrade the models, test them in different environments, and ensure rigid compatibility with VHDL 1076-1993. Please let me know of any problems.

Single Cycle SPIM  This is a model of the single cycle SPIM model from Computer Organization: The Hardware/Software Interface, by J. Hennessey and D. Patterson. The model is synthesizeable and has been tested and used in Altera's environment. Testing under Xlinx Foundation and Aldec ActiveHDL will also be (hopefully) performed soon. Note this model uses 8-bit registers and only 4 registers to make room to fit on the chips that were supported in the student version of the tools that we were using. Over the next few months I intend to grow this model to include a simulation model as well as a better documented version of the same model with a few more features that I think are useful for class projects.

Pipelined SPIM: This is a model of the pipelined SPIM model from Computer Organization: The Hardware/Software Interface, by J. Hennessey and D. Patterson. The model is synthesizeable and has been tested and used in Altera's environment. Testing under Xlinx Foundation and Aldec ActiveHDL will also be (hopefully) performed soon. Only the basic pipelined datapath is included so that students may add functionality such as forwarding and hazard detection as part of the class exercises.


If you are having problems with this page please contact  Sudhakar Yalamanchili

last revised on 4 February 2000