EE 8341a Design and Analysis of Multiprocessor Interconnection

Spring 1996 - Dr. Sudhakar Yalamanchili

3-0-3 (2S,1D) Prerequisite: EE 6760 or equivalent, and graduate standing

State of the art supercomputers rely on the interconnection of hundreds to thousands of high speed processors. Research and development of necessary interconnection networks have progressed triggered by new technologies and demands and are distinct from local and wide area communication networks. This course covers the design and analysis of such networks. The course material is vertically integrated relating aspects of the design of high speed routers, flow control protocols, and routing algorithms. Laboratory exercises will involve simulation of network architectures, routing protocols, and the evaluation of design trade-offs.

Text: Course notes, journal and conference publications

Topical Outline

• Network Topologies
• Direct Networks
• Switch-Based Networks
• Crossbar and Bus Networks
• Switching Techniques
• Circuit, Packet, and Wormhole Switching
• Virtual Channels
• Hybrid Switching Techniques such as PCS, and Buffered Wormhole.
• Comparison of Switching Techniques
• Deadlock, Livelock, and Starvation
• Theory of Deadlock Avoidance
• Deadlock Recovery Mechanisms
• Routing Algorithms
• Oblivious and Adaptive Routing
• Multicast Routing
• Fault Tolerant and Reliable Routing
• Router Architecture
• Design of oblivious and adaptive routers
• Cost/Speed Model for router architectures
• Overview of commercial routers from the Intel Paragon, Cray T3D, and IBM SP2
• Hardware support for multicast, fault tolerance, and deadlock recovery
• Messaging Layer Implementation
• Network Interface Architecture
• User Level Messaging and Buffer Management
• Network Optimization
• Physical constraints and network scaling
• Optimizing network topology and channel operation
• Emerging Trends and Open problems
• Open theoretical problems
• Impact of local area network technologies, optical communication, and workstation clusters