Summary

The NSF ERC on Packaging at Georgia Tech, under the directorship of Prof. Rao Tummala, has spawned a number of exciting breakthroughs in materials, processing technologies, circuits, algorithms, tools and architectures for advanced electronics packaging. The success and potential impact of some of these breakthroughs, e.g., embedded integrated passives, SLIM packaging structures, RF/optoelectronic integration, etc., have facilitated the proposal for a new paradigm for electronics system design for the next century --- the system-on-package (SOP). The system-on-package (SOP) paradigm elevates the role of packaging from the end of the product design cycle to early in the product specification and ASIC design. The SOP paradigm changes the current chip-centric system design methodology to a more electronics package-centric design flow. The advantages of the SOP design paradigm over the System-on-Chip (SOC) paradigm appear overwhelming on technical, business and legal fronts.

To realize these enormous advantages, the NSF ERC on Packaging at Georgia Tech has assembled together an internationally renowned team of systems architecture experts, algorithm and tool developers, and system integrators from Cornell University, North Carolina State University (NCSU), University of Arizona, IBM, Alcatel, Ericsson, and Northrup Grumman to develop the foundations of the SOP paradigm through a series of innovative research efforts combined with benchmarking for cross-validation.

The primary areas of research include integrated passives and combined electrical/physical design, high performance chip plus package design algorithms and CAD flow, signal integrity modeling and simulation, and global interconnect. A unified and integrated virtual prototyping environment for SOP will thus be realized as a result of this connectivity program, wherein complementary skills to those at the PRC are being harnessed to bring a powerful new systems design paradigm, the SOP, to life, and in a form that can enhance US competitiveness through joint collaboration with the industry.

Electronics is one of the world's largest industries, accounting for almost 1 Trillion dollars worldwide. The single most important and fundamental technology fueling this industry is that of semiconductor microelectronics. This technology has revolutionized every aspect of the electronic products in automotive, consumer, computer, telecommunications, aerospace, military and medical segments by ever higher integration of transistors at ever continued lower cost per transistor during the last four decades. These developments resulted in a capability today of more than 20 million transistors on a single chip from a wafer of 800mm produced in a plant costing about one Billion dollars. This integration and cost path has led the industry to believe that this kind of progress can go on, leading to so-called system–on-a chip (SOC), forever, and for all application areas and products - microprocessors, DSPs, wireless systems, multiprocessor servers, military systems, and computer peripherals. Our belief is that SOC is not a panacea for all product classes, other than for microprocessors and peripherals in the short time horizon, and its outlook for the long term (circa 2007) appears rife with technical, legal, and business problems. The system-on-package (SOP) is rapidly emerging as the long term solution of choice for high performance and low cost products of the future. The typical electronics product/system of the future is expected to include the following --- Digital Processors, Digital Signal Processors, Memories & ASICs, Busses and Interconnect, Peripherals and Interface Devices, Analog Baseband Front Ends, RF and Microwave Processing Stages, Discrete Components (R, L, C), Micro-Electro-Mechanical (MEMS) Components, Displays, User Interfaces, and associated logic.

Several recent studies and technology roadmaps have indicated that these electronics products of the future will be characterized by the following kinds of "heterogeneity" or "mix":

Technology Mix : Digital, Analog, RF, Optoelectronic, and Microelectromechanical, and embedded passives.

Frequency Mix: 100s of GHz in the Microwave/RF components to 100s MHz in the Digital components.

Signal Mix: Significantly higher digital circuits co-existing with ultra low-noise amplifier RF circuits.

Architectural Mix : Requirement to design for heterogeneous architectures --- event-driven, data-driven, and time-driven models of computation, regular versus irregular structures, tradeoffs required over function, form, and fit over multiple domains of computational elements and multiple hierarchies of design abstraction.

Design Mix: Electrical design to be unified with physical and thermal design across multiple levels of design abstraction.

A SOC is one where the entire system in realized on a single IC, while the SOP is a system on a package (where packages can range from chip-scale packages (CSP), to ball-grid-arrays (BGAs) to MCMs, and so on). The SOP paradigm, however, differs from MCM paradigm in a number of important ways. MCM's primary function is integration through electrical connectivity, while the SOP provides interconnectivity, functionality and performance to the target product through the packaging . The SOP paradigm, thus, involves electronics packaging in the early phases of system design, including chip/package functional partitioning and design. This represents a shift from the current chip-centric CAD flow environments pervalent in the semiconductor industry.

A vertically-integrated design environment for the future system would, typically, consist of the following interacting functional components. Its maturity may be judged through a thorough evaluation of each of the following capabilities.

Design Composition Environment: A mechanism for the capture of the requirements and specifications of the application/product in machine processable form. The SOC depends on the proposal and adoption of unified system-level description language (e.g., SLDL), while the SOP can utilize current practice specification approaches that decompose functionality and timing hierarchically.

Libraries of Design Reuse Models: Executable models of heterogeneous components, circuits, processing technologies, and materials, captured at multiple levels of abstraction (functional, pure-timing, fully-functional, clock-level, gate-level, physical/material, etc.) to assist in the co-modeling, co-simulation, and tradeoff analysis required in the translation of the specification to lower levels of abstraction. The SOC paradigm requires high quality, interoperable simulation and synthesis models at multiple levels of abstraction, supporting multiple models of computation. These design libraries or their interface standards do not exist, and those that exist are usually in hard formats (in a format that protects the IP) for legal and business reasons.

Execution Environment: The composed design specification must be executed through selective binding with models incorporated from design reuse libraries to perform the necessary tradeoffs at conceptual and detailed levels and to also carry out the design and verification tasks of the system of the future. The computational and memory requirements of the execution environment must be considered together with efficient algorithms for limiting the complexity and prescribing the accuracy/speed tradeoffs for hierarchical product co-design and verification. A unified SOC design environment would require detailed simulations of very large systems at the clock, gate and device levels, resulting in challenging requirements on the execution environment.

Interpretation & Verification Environment: The intermediate steps of the design, verification, and manufacturing phases must be interpreted continuously to measure metrics of the design synthesis and also to verify and validate the design through several iterative phases. Capabilities for check-pointing the design and capturing vital test data and applying them against the sub-system under test are required.

In the pre-SOC/SOP paradigm, the system integrator would package and assemble together on board a variety of IP functions captured as ASICs (in hard form of analog or digital variety) to form an electronics product [1]. Each of the ASICs would be supported by EDA tool environments and the fabrication/process foundries. With the rapid growth in silicon and VLSI capability, foundries are seeking to recover their investment through expanding their current range of offerings from encapsulated ASICs to systems-on-chip (SOC).

We will now outline some of the principal hurdles to realizing the System-on-Chip (SOC).

• Difficulty in capturing the requirements and composing specifications of a mixed digital/analog/RF/Microwave system in a unified and machine processable manner.
• Lack of appropriate architectural templates or experience in heterogeneous system-on-chip (SOC) implementations, including limitations of on-chip wiring in achieving adequate performance for large chips [4].
• Lack of co-design and test methodologies and tools for mixed technology design tradeoff evaluation and synthesis/verification.
• Limited libraries of models (and formats) that capture information in the materials processing, circuit design, and architectural regimes for combined modeling and design.
• Lack of design and test methodologies and tools that can carry out the tasks of partitioning, floor-planning, placement, routing, and other tasks of physical design using soft IP cores from reuse libraries. Verification at system-level is complicated by redesign at multiple levels of abstraction.
• Limited capabilities for integration of heterogeneous technologies (i.e., RF/Analog/MEMS/Microwave/Digital) and components on the same IC.
• Problems due to mechanical, thermal, and manufacturing-related (e.g., low yield for large ICs at less than 0.1 micron technologies) considerations.

• Long design and test cycles required for SOC designs in the face of changing system-level requirements during the design cycle. A SOC, by virtue of its long design cycle, may face obsolescence due to rapid product requirements creep, and thus remains a high risk investment for the foundry and the product developer.
• The need to differentiate among products (to create value) may lead to smaller volumes for SOC-based products. This vicious circle may lead to higher costs for SOC design and production.
• Integration of soft cores from reuse libraries licensed from independent sources is very difficult, and furthermore, the current business model that requires that OEM vendors release their IP in the form of the soft models to system integrators may be unlikely to succeed. Recent trends to protecting IP in models through encryption within HDL-based simulation environments may ameliorate the situation, but repartitioning the integrated system can lead to difficult system-level test cycles unless the some IP content is visible.

• The SOC changes the current product design paradigm, and places liability and legal responsibilities on the system integrator (in addition to the component/core supplier) through possible IP infringements by core suppliers. Since the SOC design phase involves significant rework and redesign of the soft cores (or derived work) by the SOC designer/vendor, indemnification contracts may be difficult to write, and may not face up to the scrutiny of a legal proceeding. As seen in by recent legal imbroglio late in the production of the V-Chip for television broadcasting, where patent disputes have surfaced at the final hour of manufacturing, it is easy to visualize such a scenario manifesting itself over and over in the SOC design community leading to higher risk relative to alternative solutions.

The SOP paradigm moves packaging design to early phases of system design including chip/package functionality partitioning and integration, which is a paradigm shift from today's system-level, or ASIC, or packaging design. Packaging has always played an important role in electronics product manufacturing at the component and board level. However, in the early days packaging's role was primarily structural in nature, and as Table 1 shows, packaging today and tomorrow is playing increasingly important roles in carrying out the product's functions and performance [3].

Packaging technologies have evolved considerably progressing from DIP and PGA (in the 1970s), QFP (in the 1980s), BGAs (in the 1990s), and to CSP (in 2000s) through new packaging architectures such as the single level integrated module board (SLIM) shown in Figure 1.

The packaging efficiency (ratio of silicon area to the system-level board) of early packaging technologies (1970s) has been very poor at about 2%, and has grown to about 40% in the 1990s [1]. For application such as cellular phones, camcorders, or magnetic disk drives, the packaging efficiency has about 10%. Newer packaging technologies, such as SLIM, promise much higher efficiencies of about 80%. They achieve this for two reasons: (1) discrete components are embedded into the packaging substrate and thus take no additional surface area on the substrate, (2) all of the integration and extensive thin film wiring allows ICs to be flip-chip bonded wall-to-wall on the substrate. This integrated module which can be a single chip, or a chipscale module that is of no greater size than the ICs themselves and can support as many as 5000 IOs.

These recent advances in packaging technology will lead to low-cost (less than a $1 per square inch) and high density (over 1000 inches per square inch of interconnect and solder bump densities of 50 um) packaging technology. These key advances lead us to seek to discover how high performance digital systems can better leverage high-density packaging.

Technical Reasons

There are significant potential strategic and tactical advantages in using high-density packaging even in the design of high performance digital systems, e.g., multiprocessor Web servers [4].

• Memory Bandwidth: Increasingly, the lack of memory bandwidth is the primary constraint for improved system performance. This constraint is especially true in multimedia and data-intensive applications. In many applications, the random nature of memory accesses result in caches being relatively ineffective and the memory bandwidth becoming the raw bandwidth related to DRAM access. This bandwidth is, in turn, limited by physical connectivity, the width of the memory fetch channel. High-density packaging will permit memory channel widths of 256 bits or more.

• Transfer of on-IC interconnect functionality to a high-density substrate: The high density substrate can be viewed as providing four or more additional layers of low-loss copper interconnect accessible through a dense solder bump ‘via’ layer. These layers can be leveraged for what are normally ‘on-chip’ interconnect functions – power/ground distribution, clock distribution and possibly key single interconnect. As a result on-chip metal is freed for other IP-related functions making the chip smaller and faster and the increased cost of test.

• Improved system integration: Non-digital functions (memory, analog) are best built in non-memory processes. Such processes can be integrated in a low-noise and low process cost fashion by integrating them on a package, rather than in a chip with additional process steps .

General electronics systems, such as cellular handsets and base-stations, which use mixed signal technologies, can exploit the SOP platform for a cost effective solution for the following reasons:

• Noise Isolation: Most wireless communication products require digital, analog and RF electronics to implement functions. Noise sensitive RF electronics are prone to failure due to the electromagnetic interference from their digital counterpart. The SOP provides an effective solution since it spreads apart the RF and digital circuits (unlike the SOC where the coupling is provided through the base silicon substrate). However, substrate coupling through the package is still possible (through planes, radiation etc) and needs to be controlled either through quiet island designs or filtering. Various methods using high density interconnect (HDI) technology for such designs may be used.
• Integrated Passive Components: In addition, since analog/RF sections of communication products are rich in passives, their integration into the substrate provides the possibility of form factor reduction and performance improvement. This is because 3-dimensional designs are possible with integral passives (using multi-layered HDI technology) with no leads necessary for connection to the circuit. However, designing with integral passives can be complex due to the parasitics that can limit performance. Hence, generation of design libraries containing passive structures is required that implies an understanding of the range of component values required, tolerance, material properties and suitable structures for integration. Considerable progress has been made in the development of these model libraries.

• SOP design cycle does not freeze the design specifications of individual components to the extent of the SOC paradigm and risk in product realization is mitigated A large market base for these technologies can also offset the investment in packaging technologies.
• The SOP product design cycle may be much shorter than the SOC design due to low risk design process. For instance, an IBM design of the G3 multiprocessor server consisting of multiple 500MHz processors with 300Mhz system clock speeds was completed in about eighteen months, while packaging design for smaller systems (e.g., portable handsets or single board computers) can be completed in a few weeks.

• SOP does not change the existing electronics product design paradigm, and IP is included at the component level. Patent and indemnification issues are not dissimilar to the current (non-SOC) board-level design arena.

At the NSF Engineering Research Center (ERC) for Low Cost Packaging (PRC) at Georgia Tech we are actively investigating new technologies for low cost design of SOPs consistent with the NEMI Technology Roadmap for Packaging (Table 2). Our three, six and ten year goals are listed in the same table, describing the goals and recent accomplishments in the following areas [2]:

Integrated Passives: The basic activities which are being carried out are: (1) systems analysis for integrated passives, (2) models to determine both integrated passives performance as well as associated parasitics magnitudes from layout geometries, and (3) technological implementation of integrated passives, including materials studies for realization of high dielectric constant, high specific resistance, and high magnetic permeability materials, as well as fabrication processes for the realization of integrated passives. The combination of these activities will allow the complete design, fabrication, and modeling of integrated passives development using low-cost fabrication processes for the realization of cost-effective electronic products.

Large Area Intelligent Manufacturing: The primary goal is to achieve high yield manufacturing on large integrated substrates consistent with 10-100x cost reduction. Yield maximization involves monitoring, modeling, and controlling each of the key integrated fabrication steps: polymer deposition, via formation, photolithography and metallization. Some recent innovations include the development of a real-time, neural network-based feedback control scheme for a general class of manufacturing processes. This approach involves process modeling with neural networks and control schemes based on parameter estimation.

Low Cost Substrate Efforts: Our vision is to reduce the cost of high density interconnection and multifunctional packaging by a factor of five and ten in approximately the same number of years. The strategy includes low cost polymers and low cost copper metallization. To validate the research effort and to provide a method to guide innovations into areas with greatest cost impact, a cost modeling technology and tools are being developed. These models are being formulated with help from industry to answer questions about the impact of low cost dielectric materials, large area processing, and novel processing steps to form integrated passives as well as lines and vias. The cost models will integrate information from the redesign of packages spurred by integrated components through the manufacturing choices available to define these components.

RF/Microwave Package Design: Ongoing research projects include the investigation of RF/microwave packaging , interconnects and low cost active packaging approaches for high performance, highly integrated, low-cost wireless systems. The goals of these projects are to develop design, analyze and characterize approaches for vertical interconnects used in RF/microwave package applications. The frequency range of interest is between 1 and 100 GHz. Other projects seek to integrate III-V semiconductor monolithic microwave ICs (MMICs) with silicon circuitry for emerging wireless applications between 1 and 100 GHz.

System-level Test: Electrical testing is one of the major cost factors in the development and manufacturing of electronic components and systems. Test costs include development costs for design and test generation, test application time, and test facilities. In order to achieve cost and performance goals for future systems, actual test costs must be reduced by a factor of between two to ten, while at the same time accommodating significantly increased circuit complexity and decreased physical (and possibly logical) accessibility. Our approach is based on large area electrical test, before and after chip assembly, and simplification of test methodologies. The PRC research is directed at three areas: (1) interconnect testing, including both bare substrates and fully populated SLIM substrates, (2) analog and mixed-signal testing, and (3) design for testability methods based on information and process models for SLIM Substrate test engineering. In order to achieve long-term cost reductions in testing, it is essential to modify the design process to incorporate testability as a key parameter. Using design for test methods in conjunction with defect data from the manufacturing process allows optimal trade-offs among cost, performance, and testability. Formal information and process modeling techniques will be used to define the basis for SLIM substrate test automation. The objective is to define information that needs to be captured during the design process and transferred to the test process, identify opportunities to integrate test generation into the design process, provide early feedback to designers regarding testability, and evaluate the potential for more efficient testing techniques.

FlipChip Assembly: The vision is to achieve 10x cost reduction and 10x in I/O performance through a number of innovative materials and assembly processes. The key to low cost in flip-chip assembly is high process throughput. While flip chip technology has been widely publicized over the last several decades, little attention has been paid to process throughput while the majority of work has concentrated on interconnect technologies. The PRC strategy is to leverage many of the advanced interconnect technologies which have emerged and to develop a systems-level low-cost flip chip process which leverages existing process technologies. The PRC roadmap for low cost, next generation flip chip processing focuses initially on low cost, high throughput processing based on area array solder interconnect systems having pitches of 250 to 150 microns. As the next generation solder process technology matures, numerous fine pitch interconnect technologies will be investigated for area array interconnect systems having pitches of 100 to 75 microns. To achieve the eleven year wafer-to-assembly cost goal of $0.0035/IO, flip chip technology for organic substrates requiring no underfill (i.e., underfill-less flip chip) is being pursued as well.

System-on-Package (SOP): The vision is to develop a design environment for mixed technology packages that integrate passives, optimize realization through an integrated chip-package level co-design process, and also focus on cutting edge applications to validate the results of the research. Our goal is to lead the path in the development of methodologies, model libraries, tools, that harness technologies developed at the PRC and elsewhere in the world to benefit US competitiveness in the SOP arena.

Recent research results in each of several thrust level activities are listed in the Figure 4. Our current goal is to integrate these new technologies into appropriate system-on-package (SOP) design, test, and manufacturing tools targeted for the SLIM-class of packages. Extensive details on these activities are available at our Web site http://www.ece.gatech.edu/research/prc.

The research strategy and activities for the groups listed in Table 2 at the PRC are shown in Figure 2.

At the NSF ERC on Packaging we have developed a number of outstanding technologies that support the SOP effort. What we need now are as follows:

1. Integration of these new packaging technologies in unified SOP design flow
2. Collaborative research with industry to transfer these technologies into applications that validate and provide feedback regarding the requirements of SOP design
3. Transfer of research result from SOP design to the university curriculum at Georgia Tech and other universities in the US.

This proposed research addresses the technical, technological, business, and legal challenges through the efforts of a world-class research consortium consisting of universities and industry. The consortia participants propose that for a large (and increasing) class of applications, the SOP paradigm affords a viable, cost-effective, and efficient realization of complex systems. The research consortium is investigating the research and development issues that will further the SOP vision, through identification of technical and other barriers to its realization, and through their resolution and benchmarking of proposed solutions. The benchmarking includes two classes of systems that are expected to dominate the internet -driven world of the next century --- (a) wireless base stations and handsets, and (b) high performance multiprocessor servers.

The NSF ERC thus proposes a new thrust area called SOP as part of its base mission leveraging all of its research that can considered SOP–related. The missing aspects of research to make the SOP complete are proposed here. The proposal does not seek funds to be expended at PRC .The PRC expects its NSF_ERC base funds to do its on-campus research and that the funds requested as part of this proposal are meant for the world-class academic partners.

The SOP thrust has identified several key technical problems that will compare and contrast the two approaches for performance, cost, reliability . The primary technical concerns are: (1) Design, Implementation, & Test of Heterogeneous and Multi-Technology Systems on Packages, and (2) Design, Implementation, & Test of High Performance Applications on a Package. The former is exemplified in the wireless base station that combines mixed and heterogeneous technologies (analog/digital/RF), and its need for conformance to rapidly changing industry standards and rapidly diminishing product cycles. The latter is exemplified in the high performance Web server, or "Giga-processor", that requires a new approach to package design to achieve its realization. These two applications are typify, in our opinion, applications that are not feasible for technical, business, and legal reasons using the SOC paradigm. The research agenda will substantiate the new technologies developed, and compare the SOP/SOC approaches through benchmarking on these applications.

Our goals are the following:

1. Develop a family of model year package architectures for the two classes of applications that conform to the growth and technology trends in these areas.
2. Develop a design environment that facilitates the design of these architectures through new integrated modeling, simulation, and synthesis capabilities for (1) Increased wiring density (including global interconnect, semiconductor metallization, and optoelectronics), (2) Accurate mixed technology modeling (RF/Analog/Digital/EM/passive/mechanical) and integration to solve a number of problems (including model development, signal contamination, passive integration), (3) Accurate design tradeoffs and system partitioning evaluation at various levels of abstraction, (4) Lower cost component integration & test methodologies and techniques (5) Improved physical design & micro-assembly technologies including integration of passives.
3. Validate and measure quality of solutions on the proposed family of architectures for the two benchmarks in collaboration with industry leaders.

SOP is highly packaging -oriented and requires the best expertise of design, fabrication, and test community in this area. Both SOP and SOC would require a integrated system-level focus to compare performance, cost, reliability and legal issues. Since the problems to be addressed are highly industry-oriented over long term, the team plans to include industry members with long term vision and experience in identifying the right problems and providing effective solutions.

The proposed outreach team possesses all these qualities. In the area of packaging expertise, it includes the two of the best and the oldest packaging centers in US: Cornell University and University of Arizona. In the area of IC and system level expertise, it includes Georgia Tech and North Carolina State University. The Industry expertise comes from two of the best IC and packaging companies: IBM and Sun, and leading system integrators such as Alcatel, Northrup Grumman, and Ericsson. These in time will be supplemented by cellular base station companies and other semiconductor companies.

The first phase of the project will be documenting current practice in the industry and identifying and ranking current technical and business challenges to packaging in the two classes of applications. This will be followed by technical SWAT teams that will address the major design hurdles through close collaboration with industry partners and a set of metrics ($ saved/handset) through the development of point tools for the problems. The third step is in the integration of the point tools to form an integrated design environment for package design, followed by testing and validation on benchmarks derived from the two classes of applications.

Specific target activities that are planned within the general flow of the timeline (Chart 1) are as follows:

• Integrated Passives and Interconnect Design: Tradeoff advisors that allow for early package design, partitioning, placement, routing, and electrical/physical design incorporating integrated passives as in SLIM. Benchmarking on Alcatel and Ericsson (to be negotiated) handsets and basestations for validation. Primary collaborators --- Cornell, Alcatel, Georgia Tech.
• Chip+Package SOP Flow: Clock, Ground, Power partitioning algorithms, advisors, and tools. Architectural performance partitioning of ASICs for optimal package design. Benchmarking on IBM's G3 server applications and derivatives. Primary Collaborators --- NCSU, IBM, University of Arizona, Georgia Tech
• Signal Integrity: Algorithms, models, simulation environments, and tools for signal integrity analysis for advanced SOP packages. Benchmarking on Northrup Grumman, IBM, and Alcatel circuits. Primary Collaborators --- NCSU, Cornell, IBM, Georgia Tech, University of Arizona.

Each consortium participant brings in unique and non-overlapping expertise to this initiative that will be vital for US competitiveness in the next decade.

Several workshops and short courses will be developed in addition to extensive technology transfer activities that will be included into the curriculum at four universities, in addition to books and technical articles over the next five years of intensive research.

1. Rao Tummala, Eugene J. Rymaszewski, Alan G. Klopfenstein (Editors), The Microelectronics Packaging Handbook, 2cnd Edition, Chapman & Hall, 1997.
2. NSF Engineering Research Center (ERC) on Low Cost Packaging Web Site, http://www.ee.gatech.edu/research/prc
3. Special Issue on "Analyzing Packaged Systems" IEEE Design & Test of Computers, July-September 1998. http://computer.org
4. E. E. Davidson, B. D. McCredie, W. V. Vilkelis, "Long Lossy Lines and Their Impact Upon Large Chip Performance," IEEE Trans. CPMT-B, Vol. 20, pp. 361-375, Nov. 1997.